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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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4.1.4.3. KR FEC Scrambler
The KR FEC scrambler block performs scrambling based on the generation polynomial, x58 + x39 +1, which is necessary for establishing FEC block synchronization in the receiver and to ensure DC balance.