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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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3.1. Key Considerations when Choosing a FEC
The primary considerations when choosing a FEC include:
- Hardware complexity
- Coding gain
- Latency
- Power
Coding Gain
Generally, the performance of a transmission line is characterized by the BER, where BER is the ratio of bits that have errors with respect to the total number of bits received over a transmission line. Additionally, the performance of a data transmission code is characterized as a function of the average energy per data bit (Eb) to noise power spectral density (N0) of the waveform. Eb can be expressed as the signal power (S) times the bit time (Tb). N0 can be expressed as the noise power (N) divided by the bandwidth. Therefore, Eb/N0 is equal to the SNR (bandwidth/bit rate).
The effectiveness of a FEC code is determined by the reduction in the Eb/N0 needed to ensure the specific BER. Coding gain is the reduction in the required Eb/N0 at the same BER for an uncoded versus a coded system. For example, an uncoded communication system operates at a BER of 10−5 at an Eb/N0 of 10 dB. Adding a strong FEC code to this communication system could reduce the ratio of Eb/N0.
Net coding gain (NCG) accounts for the bandwidth expansion needed for the FEC code, and this is associated with increased noise in the receiver side. Coding gain does not account for this. This means that the data rate had to increase by a certain percentage in order to transmit both the real data and the extra data (FEC).
Figure 3. Net Coding Gain
The lower the latency, the better it is from the application’s perspective. However, a small latency limits the block size of the FEC code, which in turn limits the performance of the code, and can also impact the decoder complexity.
The higher the clocking rate (the more redundancy you add, for example), the more coding gain you can achieve.
The larger the block size, the higher the coding gain, but also the higher the processing latency.
More parallelism reduces processing latency, but increases hardware complexity.
Figure 4. Benchmarking FEC Codes for 100GbE Applications