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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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4.1.2. FEC Block Composition
The FEC sublayer does not decrease the symbol rate of the PCS, nor does it increase the signaling rate of the PMD sublayer.
Instead, the FEC sublayer compresses the sync bits from the 64B/66B encoded data provided by the PCS to accommodate the addition of 32 parity check bits for every block of 2080 bits.
The BASE-R 64B/66B PCS maps 64 bits of scrambled payload and 2 bits of unscrambled synchronization header into 66-bit encoded blocks. The 2-bit synchronization header allows the PCS synchronization process to establish the 64B/66B block boundaries. The synchronization header is 01 for data blocks and 10 for control blocks. The synchronization header is the only position in the PCS block that always contains a transition, and this feature of the code establishes the 64B/66B block boundaries.
The FEC sublayer compresses the 2 bits of the synchronization header to one transcode bit. The transcode bit carries the state of BASE-R synchronization bits for the associated payload. This is achieved by eliminating the first bit in 64B/66B block, which is also the first synchronization bit, and preserving the second bit. The value of the second bit defines the value of the removed first bit uniquely, because it is always an inversion of the first bit. The transcode bits are further scrambled (as explained in IEEE 802.3ap Clause 74.7.4.2) to ensure DC balance.
The 32 sequential 64B/66B blocks are transcoded in this fashion, and then 32 bits of FEC parity are computed for them. The 32 transcoded words and the 32 FEC parity bits comprise a FEC block. The error detection property of the FEC cyclic code establishes block synchronization at FEC block boundaries at the receiver. If decoding passes successfully, the FEC decoder produces 32 65-bit words, the first decoded bit of each word being the transcode bit. Then, the inversion of the transcode bit constructs the first synchronization bit in the 64B/66B code, and the value of the second synchronization bit is equal to the transcode bit.