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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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5.3. 100GBASE-KP4
The 100GBASE-KP4 specification is defined in Clauses 74 and 91 of IEEE802.3bj.
100GBASE-KP4 is a non-binary code (544, 514, 15, 10). 100GBASE-KP4 features:
- 514 data symbols per codeword
- 544 data plus parity symbols per codeword
- Codeword size = 10 * 544 = 5440 bits
- Correcting capability up to 15 symbols within a codeword
- 6 to 6.5 dB gain
- PAM4 modulation
- 26.5625 Gbps bit rate
- BER of 10-12 or better (after FEC correction)