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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
Figure 17. 100GBASE-KR4 Mapping
- RS (528, 514) FEC
- Four lanes running at 25.78125 Gbps
- No rate expansion
- Data is stripped per symbol across four lanes