Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 7/08/2024
Public
Document Table of Contents

3.6. Variable Precision DSP Blocks in Cyclone® 10 GX Devices Revision History

Document Version Changes
2021.08.13
  • Added the DSP Block Cascade Limit in Cyclone® 10 GX Devices topic.
  • Removed the statements about the number of DSP blocks you can cascade as systolic FIR structure in the following topics:
    • 18-bit Systolic FIR Mode
    • 27-Bit Systolic FIR Mode
  • In the 27-Bit Systolic FIR Mode topic, removed the "Systolic registers are not required in this mode" statement. The registers are not available in the 27-bit systolic FIR mode.
Date Version Changes
May 2017 2017.05.08 Initial release.