Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 7/08/2024
Public
Document Table of Contents

7.6. Configuration, Design Security, and Remote System Upgrades in Cyclone® 10 GX Devices Revision History

Document Version Changes
2024.07.08
  • Updated the description for the following timing diagrams.
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
    • FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
    • PS Configuration Timing Waveform
  • Updated the AS Configuration Timing Waveform timing diagram.
2023.10.25 Added information about partial reconfiguration scheme.
2020.09.25 Updated Table: Available Configuration Clock Source and Transceiver Calibration CLKUSR Frequency for Cyclone® 10 GX Devices to update the supported clock sources and transceiver calibration CLKUSR frequency for AS.
2020.06.30 Updated the Active Serial Multi-Device Configuration section on determining the DCLK frequency for slave devices.
2020.03.31 Updated the User Mode topic.
2019.12.27 Added note to clarify that you should use 12 mA drive strength IBIS model when simulating the AS_DATA[0]/ASDO, AS_DATA[3:1], and DCLK configuration pins for 1.8V LVCMOS I/O standard in the I/O Standards and Drive Strength for Configuration Pins table.
2019.03.28 Updated the note in the Trace Length Guideline topic.
2019.01.24 Updated the link to the Intel® Supported Configuration Devices section of the Device Configuration - Support Center page on the Intel® website.
2019.01.07 Added link to the Configuration Devices page on the Intel FPGA website.
2018.06.14 Updated Configuration Pin Summary for Cyclone® 10 GX Devices table to indicate CLKUSR and nCEO pins are optional.
2017.11.10
  • Updated the "Configuration Schemes and Features of Intel Cyclone 10 GX Devices" table:
    • Updated the max clock rate for Passive serial (PS) scheme from 100 MHz to 125 MHz.
    • Added a footnote to the Max Data Rate value of the Configuration via Protocol [CvP (PCIe*)] scheme to show that maximum rate is limited by the PCIe protocol overhead.
  • Removed LOCK and UNLOCK instructions from Mandatory IEEE Standard 1149.1 BST JTAG Instructions.
  • Updated "Single Device FPP Configuration Using an External Host", "Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data", and "Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same Data" figures.
2017.05.08 Initial release.