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1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® 10 GX Devices
2. Embedded Memory Blocks in Cyclone® 10 GX Devices
3. Variable Precision DSP Blocks in Cyclone® 10 GX Devices
4. Clock Networks and PLLs in Cyclone® 10 GX Devices
5. I/O and High Speed I/O in Cyclone® 10 GX Devices
6. External Memory Interfaces in Cyclone® 10 GX Devices
7. Configuration, Design Security, and Remote System Upgrades in Cyclone® 10 GX Devices
8. SEU Mitigation for Cyclone® 10 GX Devices
9. JTAG Boundary-Scan Testing in Cyclone® 10 GX Devices
10. Power Management in Cyclone® 10 GX Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Cyclone® 10 GX Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Embedded Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Asynchronous Clear
2.11. Memory Blocks Error Correction Code Support
2.12. Embedded Memory Blocks in Cyclone® 10 GX Devices Revision History
3.4.1. Input Register Bank
3.4.2. Pipeline Register
3.4.3. Pre-Adder for Fixed-Point Arithmetic
3.4.4. Internal Coefficient for Fixed-Point Arithmetic
3.4.5. Multipliers
3.4.6. Adder
3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic
3.4.8. Systolic Registers for Fixed-Point Arithmetic
3.4.9. Double Accumulation Register for Fixed-Point Arithmetic
3.4.10. Output Register Bank
4.2.1. PLL Usage
4.2.2. PLL Architecture
4.2.3. PLL Control Signals
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Programmable Phase Shift
4.2.7. Programmable Duty Cycle
4.2.8. PLL Cascading
4.2.9. Reference Clock Sources
4.2.10. Clock Switchover
4.2.11. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O and Differential I/O Buffers in Cyclone® 10 GX Devices
5.2. I/O Standards and Voltage Levels in Cyclone® 10 GX Devices
5.3. Altera FPGA I/O IP Cores for Cyclone® 10 GX Devices
5.4. I/O Resources in Cyclone® 10 GX Devices
5.5. Architecture and General Features of I/Os in Cyclone® 10 GX Devices
5.6. High Speed Source-Synchronous SERDES and DPA in Cyclone® 10 GX Devices
5.7. Using the I/Os and High Speed I/Os in Cyclone® 10 GX Devices
5.8. I/O and High Speed I/O in Cyclone® 10 GX Devices Revision History
5.6.1. Cyclone® 10 GX LVDS SERDES Usage Modes
5.6.2. SERDES Circuitry
5.6.3. SERDES I/O Standards Support in Cyclone® 10 GX Devices
5.6.4. Differential Transmitter in Cyclone® 10 GX Devices
5.6.5. Differential Receiver in Cyclone® 10 GX Devices
5.6.6. PLLs and Clocking for Cyclone® 10 GX Devices
5.6.7. Timing and Optimization for Cyclone® 10 GX Devices
5.6.6.1. Clocking Differential Transmitters
5.6.6.2. Clocking Differential Receivers
5.6.6.3. Guideline: LVDS Reference Clock Source
5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
5.6.6.6. Guideline: Pin Placement for Differential Channels
5.6.6.7. LVDS Interface with External PLL Mode
5.7.1. I/O and High-Speed I/O General Guidelines for Cyclone® 10 GX Devices
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing
5.7.4. Guideline: Maximum DC Current Restrictions
5.7.5. Guideline: LVDS SERDES IP Core Instantiation
5.7.6. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
5.7.7. Guideline: Minimizing High Jitter Impact on Cyclone® 10 GX GPIO Performance
5.7.8. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.1. Key Features of the Cyclone® 10 GX External Memory Interface Solution
6.2. Memory Standards Supported by Cyclone® 10 GX Devices
6.3. External Memory Interface Widths in Cyclone® 10 GX Devices
6.4. External Memory Interface I/O Pins in Cyclone® 10 GX Devices
6.5. Memory Interfaces Support in Cyclone® 10 GX Device Packages
6.6. External Memory Interface IP Support in Cyclone® 10 GX Devices
6.7. External Memory Interface Architecture of Cyclone® 10 GX Devices
6.8. External Memory Interfaces in Cyclone® 10 GX Devices Revision History
9.1. BST Operation Control
9.2. I/O Voltage for JTAG Operation
9.3. Performing BST
9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9.6. IEEE Std. 1149.1 Boundary-Scan Register
9.7. IEEE Std. 1149.6 Boundary-Scan Register
9.8. JTAG Boundary-Scan Testing in Cyclone® 10 GX Devices Revision History
10.1. Power Consumption
10.2. Programmable Power Technology
10.3. Power Sense Line
10.4. Voltage Sensor
10.5. Temperature Sensing Diode
10.6. Power-On Reset Circuitry
10.7. Power Sequencing Considerations for Cyclone® 10 GX Devices
10.8. Power Supply Design
10.9. Power Management in Cyclone® 10 GX Devices Revision History
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10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
The following timing diagram shows the requirement of the IP core to access the voltage sensor in the core access mode when MD[1:0] is equal to 2'b11.
Timing Diagram when MD[1:0] is Equal to 2'b11
- Low-to-high transition for the corectl signal enables the core access mode.
- Wait for a minimum of two clock pulses before proceeding to step 2.
- De-asserting the reset signal releases the voltage sensor from the reset state.
- Wait for a minimum two clock pulses before proceeding to step 3.
- Configure the voltage sensor by writing into the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register for the core access mode is 8-bit wide and configuration data is shifted in serially into the configuration register.
- Specify the channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal needs to be ready before the coreconfig signal is de-asserted.
- The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register and the chsel[3:0] signal.
- Specify the next channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal needs to be ready one cycle before the eoc signal asserts. Poll the eoc and eos status signals to check if conversion for the first channel defined by the chsel[3:0] signal in step 4 is completed. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
- Repeat step 6 for all the subsequent channels.