Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 7/08/2024
Public
Document Table of Contents

7.1. Enhanced Configuration and Configuration via Protocol

Table 69.  Configuration Schemes and Features of Cyclone® 10 GX Devices Cyclone® 10 GX devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width

Max Clock Rate

(MHz)

Max Data Rate

(Mbps)

14
Decompression Design Security 15 Partial Reconfiguration 16 Remote System Update
JTAG 1 bit 33 33 Yes 17
Active Serial (AS) through the EPCQ-L configuration device

1 bit,

4 bits

100 400 Yes Yes Yes 17 Yes
Passive serial (PS) through CPLD or external microcontroller 1 bit 125 100 Yes Yes Yes 17 Parallel Flash Loader (PFL) IP core
Fast passive parallel (FPP) through CPLD or external microcontroller 8 bits 100 3200 Yes Yes Yes 18 PFL IP core
16 bits Yes Yes Yes 18
32 bits Yes Yes Yes 18
Configuration via Protocol [CvP ( PCIe* )]

x1, x2, x4 lanes

5000 19 Yes Yes Yes 17

You can configure Cyclone® 10 GX devices through PCIe* using Configuration via Protocol (CvP). The Cyclone® 10 GX CvP implementation conforms to the PCIe* 100 ms power-up-to-active time requirement.

14 Enabling either compression or design security features affects the maximum data rate. Refer to the Cyclone® 10 GX Device Datasheet for more information.
15 Encryption and compression cannot be used simultaneously.
16 Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support.
17 Partial configuration can be performed only when it is configured as internal host.
18 Supported at a maximum clock rate of 100 MHz.
19 Maximum rate is limited by the PCIe protocol overhead.