Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 7/08/2024
Public
Document Table of Contents

4.1.1. Clock Resources in Cyclone® 10 GX Devices

Table 29.  Clock Resources in Cyclone® 10 GX Devices
Clock Input Pins
Device Number of Resources Available Source of Clock Resource
  • 10CX085
  • 10CX105
  • 10CX150
  • 10CX220
  • HSSI: 4 differential
  • I/O: 32 single-ended or 16 differential
For high-speed serial interface (HSSI): REFCLK_GXB[L][1][C,D]_CH[B,T][p,n] pins

For I/O: CLK_[2A, 2J, 2K, 2L, 3A, 3B]_[0,1][p,n] pins

GCLK Networks
Device Number of Resources Available Source of Clock Resource
All 32
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • Fractional PLL (fPLL) and I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • REFCLK and clock input pins
  • Core signals
  • Phase aligner counter outputs
RCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10CX085
  • 10CX105
  • 10CX150
  • 10CX220
8
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL and I/O PLL C counter outputs
  • I/O PLL M counter outputs for feedback
  • REFCLK and clock input pins
  • Core signals
  • Phase aligner counter outputs
SPCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10CX085
  • 10CX105
  • 10CX150
  • 10CX220
144 For HSSI:
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL C counter outputs
  • REFCLK and clock input pins
  • Core signals

For I/O:

  • DPA outputs (LVDS I/O only)
  • I/O PLL C and M counter outputs
  • Clock input pins
  • Core signals
  • Phase aligner counter outputs
LPCLK Networks
Device Number of Resources Available Source of Clock Resource
  • 10CX085
  • 10CX105
  • 10CX150
  • 10CX220
24 For HSSI:
  • Physical medium attachment (PMA) and physical coding sublayer (PCS) TX and RX clocks per channel
  • PMA and PCS TX and RX divide clocks per channel
  • Hard IP core clock output signals
  • DLL clock outputs
  • fPLL C and M counter outputs
  • REFCLK and clock input pins
  • Core signals

For I/O:

  • DPA outputs (LVDS I/O only)
  • I/O PLL C and M counter outputs
  • Clock input pins
  • Core signals
  • Phase aligner counter outputs

For more information about the clock input pins connections, refer to the pin connection guidelines.