Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.3. MAX 10 System Controller

The highlights of the MAX® 10 devices include:
  • Internally stored dual configuration flash
  • User flash memory
  • Instant on support
  • Integrated analog-to-digital converter (ADC)
  • Single-chip Nios II soft core processor support

MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Table 10.   Summary of Features for MAX® 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology
Packaging
  • Low cost, small form factor packages—support multiple packaging technologies and pin pitches
  • Multiple device densities with compatible package footprints for seamless migration between different device densities
  • RoHS6-compliant
Core architecture
  • 4-input look-up table (LUT) and single register logic element (LE)
  • LEs arranged in logic array block (LAB)
  • Embedded RAM and user flash memory
  • Clocks and PLLs
  • Embedded multiplier blocks
  • General purpose I/Os
Internal memory blocks
  • M9K—9 kilobits (Kb) memory blocks
  • Cascadable blocks to create RAM, dual port, and FIFO functions
User flash memory (UFM)
  • User accessible non-volatile storage
  • High speed operating frequency
  • Large memory size
  • High data retention
  • Multiple interface option
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes
  • Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines
ADC
  • 12-bit successive approximation register (SAR) type
  • Up to 16 analog inputs
  • Cumulative speed up to 1 million samples per second (MSPS)
  • Integrated temperature sensing capability
Clock networks
  • Global clocks support
  • High speed frequency in clock network
Internal oscillator Built-in internal ring oscillator
PLLs
  • Analog-based
  • Low jitter
  • High precision clock synthesis
  • Clock delay compensation
  • Zero delay buffering
  • Multiple output taps
General-purpose I/Os (GPIOs)
  • Multiple I/O standards support
  • On-chip termination (OCT)
  • Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter
External memory interface (EMIF) Supports up to 600 Mbps external memory interfaces:
  • DDR3, DDR3L, DDR2, LPDDR2
  • SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (–6 or –7). Refer to the MAX® 10 FPGA Device Datasheet or the External Memory Interface Spec Estimator webpage for more details.
Configuration
  • Internal configuration
  • JTAG
  • Advanced Encryption Standard (AES) 128-bit encryption and compression options
  • Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes
  • Single- and dual-supply device options
  • Dynamically controlled input buffer power down
  • Sleep mode for dynamic power reduction
Related Information
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