Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.9.6. 10/100/1000Base-T Ethernet Connector

A copper Ethernet connector (RJ1) is provided on the PCIe bracket. This interface is implemented with Marvell 88E1111 10/100/1000Base-T Ethernet PHY.

The interface to FPGA is with SGMII through a pair of LVDS on FPGA. The PHY is managed with MDC/MDIO management interface. The signals used and hardware configuration pins of the Marvell device are shown in the table below:
Table 23.  JTAG DIP Switch Settings
Hardware Configuration Pins Connection Bits Bit [2] Bit [1] Bit [0]
Config0 GND 000 PHYADR [2:0] = 000
Config1 GND 000 ENA_PAUSE = 0 PHYADR [4:3] = 00
Config2 VDDO 111 ANEG [3:1] = 111
Config3 GND 000 ANEG [0] = 0 ENA_XC = 0 DIS_125 = 0
Config4 LED_1000 100 HWCFG_MODE [2:0] = 100
Config5 LED_10 110 DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MODE [3] = 0
Config6 LED_RX 010 SEL_TWSI = 0 INT_POL = 1 75/50 OHM = 0
The default hardware configuration is
  • Select MDC/MDIO interface. PHY address is 5'b00000.
  • INTn signal is active low
  • 50 Ohm termination for SGMII
  • Disable fiber/copper auto selection
  • Hardware Configuration mode is "SGMII without Clock with SGMII Auto-Neg to copper"
  • Energy detect is disabled
  • Disable crossover
  • PAUSE is disabled

The registers of the Marvell 88E1111 device can be changed with MDC/MDIO. The MDC/MDIO is connected to the FPGA device through a level translator.

Level Two Title