Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.2. Cyclone® 10 GX FPGA

The target FPGA device this kit is designed to work with is the Cyclone® 10 GX 10CX220YF780E5G FPGA. It is the device with the fastest speed, largest resource and biggest package in the Cyclone® 10 GX FPGA series.

Table 8.  Maximum Resource Availability
Feature Count
FPGA Device 10CX220YF780E5G
Logic Elements (LE) 220K
ALM 80,330
Registers 321,320
Memory - M20K 11,740 Kb
Memory - MLAB 1,690
Variable precision DSP block 192
18 x 19 Multiplier 384
Hard Floating-point Arithmetic Yes
PLL (Fractional Synthesis) 4
PLL (I/O) 6
12.5 Gbps Transceiver 12
GPIO 284
LVDS Pair 118
PCIe Hard IP Block 1
Hard Memory Interfaces 2
Package F780 (29 mm x 29 mm)

The table below presents a summary of the Cyclone® 10 GX FPGA I/O resource allocation. I/O Direction is with respect to the FPGA.

Table 9.   Cyclone® 10 GX FPGA I/O Resources Table
Bank Number Function I/O Type I/O Count Description
Transceiver Clocks
1C USB_REFCLK   2 125 MHz (adjustable), AC
1C FMC_GBTCLK_M2C LVDS input 2 User-defined from FMC, AC
1D SFP_REFCLK LVDS input 2 644.53125 MHz (adjustable), AC
1D PCIE_REFCLK LVDS input 2 100 MHz from PCIe* , DC
Transceiver Channels
1C/1D PCIE_TX[0:3] CML output 8(4p) PCIe* Gen2 Transmit
1C/1D PCIE_RX[0:3] CML/LVDS input 8(4p) PCIe* Gen2 Receive
1D SFP+_TX[0:1] CML output 4(2p) SFP+ Transmit
1D SFP+_RX[0:1] CML / LVDS input 4(2p) SFP+ Receive
1D USB31_TX CML output 2(1p) USB3.1 Transmit
1D USB31_RX CML/LVDS input 2(1p) USB3.1 Receive
1C/1D FMC_DP_C2M[0:4] CML output 10(5p) FMC Transmit
1C/1D FMC_DP_M2C[0:4] CML/LVDS input 10(5p) FMC Receive
Global FPGA Clocks
2A M10_USB_CLK 1.8 V CMOS input 1 30/48 MHz from U2 ( MAX® 10)
2A C10_REFCLK1 LVDS input 2 125 MHz (adjustable)
2L C10_CLK50M 1.8 V CMOS input 1 50 MHz OSC, free running
2L C10_REFCLK2 LVCMOS input 2 100 MHz (adjustable)
2J REFCLK_EMIF LVDS input 2 21.186 MHz (adjustable)
Global FPGA Reset
2A FPGA_RESETn 1.8 V CMOS input 1 From U2 ( MAX® 10)
JTAG
CSS C10_TCK 1.8 V CMOS input 1 From U2 ( MAX® 10)
CSS C10_TMS 1.8V CMOS input 1 From U2 ( MAX® 10)
CSS C10_TDI 1.8 V CMOS input 1 From U2 ( MAX® 10)
CSS C10_TDO 1.8 V CMOS input 1 To U2 ( MAX® 10)
Configuration
2A C10_CLKUSR 1.8 V CMOS input 1 100 MHz, for calibration
CSS C10_MSEL[0:1] 1.8 V CMOS input 2 From DIP Switch S1
CSS C10_nSTATUS 1.8 V CMOS output 1 To U2/U3 ( MAX® 10)
CSS C10_CONF_DONE 1.8 V CMOS output 1 To U2/U3 ( MAX® 10)
CSS C10_nCONFIG 1.8 V CMOS input 1 From U2 ( MAX® 10)
CSS C10_CS0n 1.8 V CMOS output 1
  • Power Solution 2: To U4 (MT25Q)
  • Power Solution 1: To U4 (EPCQ-L)
CSS C10_AS_D[0:3] 1.8 V CMOS inout 4
  • Power Solution 2: To U4 (MT25Q)
  • Power Solution 1: To U4 (EPCQ-L)
CSS C10_DCLK 1.8 V CMOS inout 1 For ASx4:
  • Power Solution 2: To U4 (MT25Q)
  • Power Solution 1: To U4 (EPCQ-L)

For FPPx16: From U3 ( MAX® 10)

2A FPP[0:15] 1.8 V CMOS input 16 From U3 ( MAX® 10)
2A CVP_CONFDONE 1.8 V CMOS output 1 To U2 ( MAX® 10)
UBII Side Bus
2A M10_USB_DATA[0:7] 1.8 V CMOS input 8 From U2 ( MAX® 10)
2A M10_USB_ADDR[0:1] 1.8 V CMOS input 2 From U2 ( MAX® 10)
2A M10_USB_RDn 1.8 V CMOS input 1 From U2 ( MAX® 10)
2A M10_USB_WRn 1.8 V CMOS input 1 From U2 ( MAX® 10)
2A M10_USB_RESETn 1.8 V CMOS input 1 From U2 ( MAX® 10)
2A M10_USB_FULL 1.8 V CMOS output 1 From U2 ( MAX® 10)
2A M10_USB_EMPTY 1.8 V CMOS output 1 From U2 ( MAX® 10)
2A M10_USB_Oen 1.8 V CMOS input 1 From U2 ( MAX® 10)
2A M10_USB_SCL 1.8 V CMOS input 1 From U2 ( MAX® 10)
2A M10_USB_SDA 1.8 V CMOS inout 1 From U2 ( MAX® 10)
EMIF
2J DDR3_A[0:14] 1.5 V SSTL output 15 To U12/U13/U14 DDR3
2J DDR3_BA[0:2] 1.5 V SSTL output 3 To U12/U13/U14 DDR3
2J DDR3_RASn 1.5 V SSTL output 1 To U12/U13/U14 DDR3
2J DDR3_CASn 1.5 V SSTL output 1 To U12/U13/U14 DDR3
2J DDR3_WEn 1.5 V SSTL output 1 To U12/U13/U14 DDR3
2J DDR3_CK 1.5 V SSTL output 2 To U12/U13/U14 DDR3
2J DDR3_CKE[0:1] 1.5 V SSTL output 2 To U12/U13/U14 DDR3
2J DDR3_ODT[0:1] 1.5 V SSTL output 2 To U12/U13/U14 DDR3
2J DDR3_CS[0:1] 1.5 V SSTL output 2 To U12/U13/U14 DDR3
2J DDR3_RSTn 1.5 V CMOS output 1 To U12/U13/U14 DDR3
2J/2K DDR3_D[0:39] 1.5 V SSTL inout 40 To U12/U13/U14 DDR3
2J/2K DDR3_DQS[0:4] 1.5 V SSTL inout 10 To U12/U13/U14 DDR3
FMC LVDS GPIO
3A/3B FMC_LA_TX[0:16] Vadj CMOS inout 34 To J7 (FMC), DC
3A/3B FMC_LA_RX[0:14] Vadj CMOS inout 30 To J7 (FMC), DC
3A/3B FMC_LA_CC[0:1] Vadj CMOS input 4 From J7 (FMC), DC
3A/3B FMCA_CLK_M2C[0:1] Vadj CMOS input 4 From J7 (FMC), DC
3B FMC_PRSN_1V8 Vadj CMOS input 1 From J7 (FMC)
3A FMC_SCL Vadj CMOS output 1 To J7 (FMC)
3A FMC_SDA Vadj CMOS inout 1 To J7 (FMC)
10/100/1000 Base-T
2A SGMII_TXP/N LVDS output 2 To U33 (88E1111 PHY), AC
2A SGMII_TXP/N LVDS input 2 To U33 (88E1111 PHY), AC
2L ETH_MDC_C10 1.8 V CMOS output 1 To U33 (88E1111 PHY)
2L ETH_MDIO_C10 1.8 V CMOS inout 1 To U33 (88E1111 PHY), AC
2L ETH_INTn_C10 1.8 V CMOS input 1 To U33 (88E1111 PHY), AC
2L ETH_RESETn_C10 1.8 V CMOS output 1 To U33 (88E1111 PHY), AC
SFP+ sideband
2L SFP_SCL_0 1.8 V CMOS output 1 To J5 (SFP+ 0)
2L SFP_SDA_0 1.8 V CMOS inout 1 To J5 (SFP+ 0)
2L SFP_INT_0 1.8 V CMOS input 1 To J5 (SFP+ 0)
2L SFP_SCL_1 1.8 V CMOS output 1 To J6 (SFP+ 1)
2L SFP_SDA_1 1.8 V CMOS inout 1 To J6 (SFP+ 1)
2L SFP_INT_1 1.8 V CMOS input 1 To J6 (SFP+ 1)
PCIe* sideband
2L PCIE_WAKEn 1.8 V CMOS input 1 To golden finger, reserved
2L PCIE_SMBCLK 1.8 V CMOS output 1 To golden finger
2L PCIE_SMBDAT 1.8 V CMOS inout 1 To golden finger
2A PCIE_PERSTn 1.8 V CMOS input 1 To golden finger
ULPI (USB 2.0)
2L USB_D[0:7] 1.8 V CMOS inout 8 To U32 (USB Transceiver)
2L USB_NXT 1.8 V CMOS input 1 To U32 (USB Transceiver)
2L USB_DIR 1.8 V CMOS input 1 To U32 (USB Transceiver)
2L USB_STP 1.8 V CMOS output 1 To U32 (USB Transceiver)
2L USB_CLK 1.8 V CMOS output 1 60 MHz, REFCLK for ULPI
2L USB_RESETn 1.8 V CMOS output 1 To U32 (USB Transceiver)
USB3.1 sideband
2L USB_SCL 1.8 V CMOS output 1 To U26 (USB3.1 Transceiver Switch)
2L USB_SDA 1.8 V CMOS inout 1 To U26 (USB3.1 Transceiver Switch)
2L USB_PWEN 1.8 V CMOS output 1 To U25 (USB3.1 Transceiver Switch)
2L USB_SW_INTn_1.8V 1.8 V CMOS input 1 To U26 (USB3.1 Transceiver Switch)
2L USB_ID_1.8V 1.8 V CMOS input 1 To U26 (USB3.1 Transceiver Switch)
QSPI Flash
2L C10_QSPI_CSn 1.8 V CMOS output 1 To U58 (QSPI Flash)
2L C10_QSPI_RESETn 1.8 V CMOS output 1 To U58 (QSPI Flash)
2L C10_QSPI_CLK 1.8 V CMOS output 1 To U58 (QSPI Flash)
2L C10_QSPI_D[0:3] 1.8 V CMOS inout 4 To U58 (QSPI Flash)
Level Two Title