Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.4. FPGA Configuration

JTAG

The JTAG topology of the board is shown in the figure below. An on-board Intel® FPGA Download Cable is implemented with the MAX® 10. It is in the form of a micro-USB type-B connector (J9).

Figure 19. JTAG Topology Block Diagram

The system MAX® 10 device itself can be configured through on-board USB port or an external Intel® FPGA Download Cable II header. the 2x5 header for MAX® 10 is not mounted by default.

A secondary MAX® 10 device is used for PFL configuration mode. This CFG MAX® 10 is configured with on-board USB port.

The Cyclone® 10 GX FPGA device is configured with on-board USB port or an external Intel® FPGA Download Cable II header.

The FMC interface also has a JTAG interface. The FMC JTAG can also be included into the JTAG chain.

The Cyclone® 10 GX device JTAG and FMC JTAG can be put included or isolated from the JTAG chain by setting a DIP switch S5.

Table 11.  JTAG DIP Switch Settings
Switch Signal Function
S5.1 FMC_JTAGEN ON - Disable JTAG
S5.2 C10_JTAGEN ON - Disable JTAG

Configuration

The Cyclone® 10 GX FPGA device can be configured using different modes. Mode selection can be done using DIP switch S1.

Table 12.  Configuration Mode Settings
Configuration Scheme VCCPGM (V) Power-On Reset Delay Valid MSEL [2:0]
JTAG-based Configuration ----- ------ Use any valid MSEL pin settings given below
AS (x1 and x4) 1.8 Fast 010
Standard 011
PS and FPP (x8, x16, x32) 1.2 / 1.5 / 1.8 Fast 000
Standard 001
Table 13.  MSEL Switch S1 Definition
Switch Signal Note
S1.1 C10_MSEL0

MSEL2 is tied to GND

ON - '0'
S1.2 C10_MSEL1
Figure 20. FPGA Configuration Scheme Block Diagram

The Cyclone® 10 GX FPGA device is configured with two modes: ASx4 or FPP x16. The AS x4 mode uses an MT25Q (for Power Solution 2)/ EPCQ-L 1024 (for Power Solution 1) to store the image. A dedicated MAX® 10 device is used to implement PFL. It interfaces with two pieces of x16 parallel NOR flash devices to get a x32 bus width. The highest density is 2 Gb. The flash interface works at 3.3 V and various NOR flashes from different vendors can be used with this board.

Micron MT28EW01GABA1LPC-0SITES is installed in manufacturing by default. 2 Gb is provided with the board.

For the Cyclone® 10 GX FPGA device, the image size is less than 85 Mb. Multiple images can be stored and selected by the user. The image to be used can be selected with a group of Push Buttons and LEDs.

The user can select between the images to be loaded into Cyclone® 10 GX FPGA.
  • Cycling images by pushing button S7
  • CFG MAX® 10 device displays current number to be used with LEDs D16-D18
  • Initiate the reconfiguration by pushing button S12
The signal definition of these buttons and LEDs are shown below:
Table 14.  Program Selection Signals Definition
Switch / LED Signal Note
S7 PGM_SEL Select program
S12 SYS_CONFIG_PB Reconfigure
D16 PGM_LED0 PGM_LED [2:0] indicates the program to be used
D17 PGM_LED1
D18 PGM_LED2

Side Bus

A group of Side Bus signals are defined between MAX® 10 and Cyclone® 10 GX FPGA device to provide a higher speed access through on-board Intel® FPGA Download Cable. This interface is reserved in hardware.

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