Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab Board Information System MAX Control JTAG Chain 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

4.3.2. The System Info Tab

The System Info tab shows the board's current configuration. The tab displays the contents of the MAX® 10 registers, the JTAG chain, the board's MAC address, and other details stored on the board.

Figure 7. The System Info Tab

The following sections describe the controls of the System info tab

Board Information

The Board Information control displays static information about your board:
  • Board Name: Indicates the official name of the board given by BTS
  • Board P/N: Indicates the part number of the board
  • Serial Number: Indicates the serial number of the board
  • Board Revision: Indicates the revision of the board
  • MAC Address: Indicates MAC Address of the board

System MAX Control

MAX Ver: Indicates the version of MAX® 10 code currently running on the board.

The MAX® 10 code resides in the <package dir>\examples\max10 directory. Newer revisions of this code may be available on the Cyclone® 10 GX FPGA Development kit link on the Intel website.

The MAX® 10 register control allows you to view and change the current MAX® 10 register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 5.  MAX 10 Registers
MAX 10 Register Values Description
Configure Resets the system and reloads the FPGA with a design from the CFI flash memory based on the other MAX® 10 register values. It works only in FPP mode.
PSO Sets the MAX® 10 PSO register.
PSR Sets the MAX® 10 PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA configuration.
PSS Displays the MAX® 10 PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.

JTAG Chain

The JTAG chain shows all the devices currently in the JTAG chain.

Note: System MAX and FPGA should all be present in the JTAG chain when running BTS GUI.
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