Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.6. Clocks

Figure 21. Clock Distribution

The Cyclone® 10 GX FPGA local clocks are generated with Si570 + Si53307 + Si5332.

Si570 is a programmable oscillator. It is configurable with an I2C interface at address 7'b110_0110. Si53307 is a clock buffer. With Si570 + Si53307, a high frequency reference clock at frequency up to 725 MHz is available for Cyclone® 10 GX FPGA Transceiver. Other clocks are generated with an programmable clock generator Si5332 at I2C address 7'b110_1010.

Features of Si5332

  • Output frequency Range: 5 MHz to 312.5 MHz differential
  • Input frequency Range: 10 MHz to 250 MHz differential, 16 MHz to 30 MHz external crystal
  • Embedded 50 MHz crystal option for 8 or 12 port devices
  • MultiSynth technology enables any frequency synthesis on any output up to 250 MHz
  • Highly configurable output path featuring a cross-point multiplexer
    • Up to three independent fractional synthesis output paths
    • Up to five independent integer dividers
    • The Input Reference Clock
  • Low Phase Jitter: 400 fs rms max
  • Programmable spread spectrum
  • 1.8 V, 2.5 V, 3.3 V core VDD
  • 1.8 V, 2.5 V, 3.3 V differential output

A local free running 100 MHz oscillator is used to generate the reference clock for calibration. This clock is also used by ASx4 configuration. A free running 50 MHz oscillator is used to generate a reference clock for FPGA core.

The MAX® 10 works with free running 50 MHz oscillator. Adjusting the variable clocks does not affect the working of the MAX® 10 device.

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