Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

This development kit includes a Cyclone® 10 GX FPGA device along with the following components.

Cyclone® 10 GX FPGA

  • Cyclone® 10 GX FPGA device in F780 BGA package
  • 780 pin, 29 mm x 29 mm BGA package
  • 220K Logic Elements (LEs)
  • 12 transceivers capable of 12.5 Gbps data rates
  • 284 GPIOs with 118 pairs of LVDS

FPGA Configuration

  • Active Serial (ASx4) mode configuration with MT25Q (for Power Solution 2)/EPCQ-L (for Power Solution 1)
  • Fast Passive Parallel (FPP) mode configuration mode by MAX® 10 PFL
  • Configuration via PCIe* (CvP) x4 Gen2

Clock Sources

  • 50 MHz oscillator, LVCMOS for Intel® FPGA Download Cable and Power MAX® 10 logic
  • 50 MHz oscillator, LVCMOS for Parallel Flash Loader (PFL) control MAX® 10 logic
  • 24 MHz crystal for Intel® FPGA Download Cable II PHY
  • 50 MHz oscillator, LVCMOS for Cyclone® 10 GX FPGA core
  • 100 MHz oscillator, LVCMOS for Cyclone® 10 GX FPGA user_clk
  • A programmable oscillator, LVDS for tranceivers: 644.53125 MHz by default, LVDS to FPGA tranceiver
  • Programmable clock generator for FPGA logic
    • 21.186 MHz LVDS for EMIF, LVDS to FPGA core
    • 125 MHz LVDS for transceiver of USB3.1, LVDS to FPGA transceiver
    • 125 MHz for Gigabit Ethernet, LVDS to FPGA core
    • 100 MHz for FPGA logic, LVCMOS to FPGA core
  • 100 MHz for PCIe* system to FPGA transceiver
  • User-defined reference clock input from FMC card
    • 1 for FMC transceiver to FPGA transceiver
    • 2 for FMC LA reference to FPGA core
    • 2 for FMC clock reference to FPGA core
  • One external differential input through SMA, AC coupled
  • One single-ended LVCMOS clock output through SMA, DC coupled

Transceiver Interfaces

  • 12 transceivers organized in two banks
  • 4 channels for PCIe* x4 Gen2
  • 2 channels for 2 SFP+ supporting 10 GE
  • 1 channel for USB3.1 SuperSpeed
  • 5 channels for FMC card

Memory Interfaces

  • 1 channel of x40 DDR3 @ 933 MHz

Communication Ports

  • 10/100/1000Base-T Ethernet port with SGMII (LVDS)
  • USB3.1 Type-C supporting SuperSpeed, backward compatible with USB2.0
  • 2 SFP+ supporting 10GE
  • FMC expansion card:
    • 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
    • 8G DisplayPort: Bitec FMC DisplayPort Daughter Card
    • 6G HDMI 2.0: Bitec FMC HDMI Daughter Card

Pushbuttons

  • 3 User Push Buttons
  • 1 User Program selecting Pushbutton
  • 1 nCONFIG Pushbutton to initiate configuration
  • 1 FPGA reset Pushbutton to reset the FPGA logic

Switches

  • 4 User DIP Switches
  • DIP switch for MSEL
  • DIP switch for JTAG chain selection
  • DIP switch for clock source selection

LEDs

  • 4 User LEDs
  • 1 Power LED
  • 1 Config Done LED
  • PFL Load/Error LED
  • PFL Program Number LED
  • Ethernet LEDs
  • SFP+ LEDs

Heatsink and Fan

Heatsink with fan

Power

  • 12 V power input from ATX 2 x 4 power connector
  • 12 V external power adaptor input
  • 12 V power input from PCIe* system
  • On/Off Slide Power Switch
  • On-board power measurement and management
  • Adjustable FMC+ power regulator
  • Power Failure Monitor
  • Power-off discharge circuit

Dimensions

Full height PCIe* add-in card 4.376" (Height) x 7" (Length)

Operating Environment

Ambient Temperature: 0° C to 45° C

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