Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.9.3. SFP+ Interface

Two SFP+ connectors (J5, J6) are provided on the PCIe* bracket. Each connector supports a 10 GE SFP+ hot pluggable module.

Each SFP+ interface has the following signals:
  • Transceivers, x1 for each SFP+, up to 12.5 Gbps
  • SMBUS (I2C), 3.3 V for SFP+ and I/O expander, level-translated 10 1.8-V with U22/U23
  • IRQ of I/O expander, 3.3 V level-translated to 1.8 V with U19

Each SFP+ module has six status/control signals and two LEDs. The FPGA device does not have enough I/O pins for these signals, hence an I/O expander is used to implement these I/Os for each SFP+ connector. The I2C I/O expander is on the same I2C bus as the SFP+ module, and the I2C bus of two SFP+ modules are independent of each other.

The I/O expander used is TI TCA9534PWR. U20 is for SFP+ 0, with I2C address 7'b010_0000. U21 is for SFP+, with I2C address 7'b010_0000.

The I/O expander has 8 I/Os. The definition of the I/Os is shown in the table below. The device is controlled with I2C bus.

Table 21.  I/O Expander: I/O Definition
I/O Number Signal I/O Type Function
P0 SFP_RLED Output Red LED, indicates LOS/ERR, "0" - ON
P1 SFP_GLED Output Green LED, indicates Link, "0" - ON
P2 SFP_TXDIS Output Tx_Disable, Pulled up, Transmitter is turned off if high
P3 SFP_TFLT Input Tx_Fault, Pulled up, indicates fault when high
P4 SFP_RS1 Output Rate Select, Pulled up with 1K resistor
P5 SFP_RLOS Input Rx_LOS, Pulled up, indicates LOS when high
P6 SFP_RS0 Output Rate Select, Pulled up with 1K resistor
P7 SFP_PRSN Input Mod_ABS, Pulled up, module in place when low

The I/Os of TCA9534 is in high impedance input mode upon power up. Hence, the module is placed in TX_Disable mode and the LEDs are off. The status changes on the I/Os are reported with an IRQ to the FPGA. Each I/O expander has its own dedicated IRQ signal.

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