A.1. Board Overview
- Cyclone® 10 GX FPGA and its peripherals
- Configuration with MAX® 10 FPGA
- Timing
- Power Supply
Board Reference | Type | Description |
---|---|---|
Featured Devices | ||
U1 | FPGA | Cyclone® 10 GX FPGA 10CX220YF780E5G, 220K Logic Elements, 12 Transceivers, F780 BGA package. |
U2 | FPGA | MAX® 10 10M08SAU169C8G for On-board Intel® FPGA Download Cable II and Power Management. |
U3 | FPGA | MAX® 10 10M08SAU169C8G for PFL configuration, clock generator control and power monitoring. |
Power Solution 2 | ||
U49 | Voltage Regulator | MPS MPM3690GBF-50D-0011, 50 A Integrated Power Module with PMBus interface, implements FPGA 0.9 V Vcc. |
U50 | Voltage Regulator | MPS MPM3695GRF-25-0037, 20 A Integrated Power Module with PMBus interface, implements 3.3V intermediate power bus used by other lower voltage power rails and 3.3_stby power supply used by U2 and U3. |
U51, U62 | Voltage Regulator | MPS MPM3632SGPQ-C879-Z -3A synchronous, rectified, step-down, mini-module regulator with built-in power MOSFETs and inductor, implements 5V USB VBUS of USB3.1 Type-C interface. |
U52 | Voltage Regulator | MPS MPM3612GLQ-C879-Z -1A synchronous, rectified, stepdown, switch-mode converter with built-in internal power MOSFETs and high light-load efficiency, implements local power supply used by Temperature sensor U46. |
U53, U54, U55, U56, U60 | Voltage Regulator | MPS MPM3650CGQW-C879-Z -6A fully integrated high frequency, synchronous, rectified, step-down power module with an internal inductor, 0.95 V, 1.03 V,1.5 V, and 1.8 V power rails to FPGA. |
U15 | DDR Termination Regulator | TI TPS51200 Sink and Source DDR Termination Regulator, implements 0.75 DDR3 VTT voltage. |
U8 | Linear Regulator | MPS MP20051DQ-LF-C879-Z, Low Noise, High PSRR, 1A Linear Regulator. |
U36, U37 | Voltage Regulator | MPS MPM3804GG-C879-Z – 0.6 A DC-DC module that includes a monolithic, step-down, switch-mode converter with built-in, internal power MOSFETs and an inductor, implements 1 V and 2.5 V voltages to Ethernet PHY device. |
Power Solution 1 | ||
U49 | Voltage Regulator | Intel® Enpirion® EM2130L-30A Step-Down DC-DC Switching Converter with Integrated Inductor, featuring Digital Control with PMBus™ v1.2 Compliant Interface, implements FPGA 0.9 V Vcc. |
U50 | Voltage Regulator | Intel® Enpirion® EM2130H – 30A Step-Down DC-DC Switching Converter with Integrated Inductor, Featuring Digital Control with PMBus™ v1.2 Compliant Interface, implements 3.3 V intermediate power bus used by other lower voltage power rails. |
U51 | Voltage Regulator | Intel® Enpirion® ER2120QI - 2A Synchronous Buck. Regulator with Integrated MOSFETs, implements 5 V USB VBUS of USB3.1 Type-C interface. |
U52 | Voltage Regulator | Intel® Enpirion® ER3105DI - 500mA Wide VIN Synchronous Buck Regulator, implements local power supply used by U49 and U50. |
U53, U54, U55, U60 | Voltage Regulator | Intel® Enpirion® EN6337QI - 3A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor, implements 1.03 V, 1.5 V, and 1.8 V power rails to FPGA. |
U56 | Voltage Regulator | Intel® Enpirion® EN6347QI - 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor, implements voltage adjustable power rail to FPGA and FMC daughter card |
U62 | Voltage Regulator | Intel® Enpirion® ER3110DI - 1A Wide VIN Synchronous Buck Regulator, implements power supply used by U2 and U3. |
Configuration and Setup Elements | ||
J9 | Embedded Intel® FPGA Download Cable II | Type-B Micro USB Connector for programming and debugging the FPGA |
J11 | 10-pin header | Optional JTAG direct via 10-pin header for external download cables |
S1 | DIP-SW: ON/Closed/0 OFF/Open/1 |
Cyclone® 10 GX FPGA Configuration Mode |
S7 | FPGA PGM_SEL Push Button | Press this button to cycle through different PFL loads. |
S12 | FPGA nCONFIG Push Button | Press this button to trigger reconfiguration. |
S13 | FPGA Reset Push Button | Press this button to reset all registers in the FPGA. |
Status Elements | ||
D23 | Power LED (Green) | Power Good LED (All power rails are OK) ON: Detected Power is Good OFF: Detected Power is Bad |
D13 | Configuration Error LED (Red) | Config error status Indicator ON: FPGA configuration failed OFF: FPGA configured without error |
D14 | Load LED (Green) | Config is loading ON: FPGA configuration is going on OFF: FPGA configuration has finished |
D15 | Configuration LED (Green) | Config done status Indicator ON: FPGA configured successfully OFF: FPGA not configured |
General User Input/Output | ||
S8, S10, S11 | General user push buttons | Three user push buttons. Driven low when pressed. |
D19, D20, D21, D22 | User LEDs | Four user LEDs. Illuminates when driven low. |
S9, S15 | User DIP Switches | 4-bit user DIP switches, low when set to ON. |
Clocks | ||
U11 | 50 MHz Oscillator | 50 MHz crystal oscillator for logic of two MAX® 10 FPGA devices, 3.3 V LVCMOS. |
Y4 | 50 MHz Oscillator | 50 MHz crystal oscillator for general purpose logic of Cyclone® 10 GX FPGA, 1.8 V LVCMOS. |
Y1 | 100 MHz Oscillator | 100 MHz crystal oscillator for calibration and configuration of Cyclone® 10 GX FPGA, 1.8 V LVCMOS. |
Y2 | Programmable Oscillator | Programmable Oscillator for Cyclone® 10 GX FPGA Transceivers, LVDS. |
U7 | Clock Buffer | 2:1 buffer for reference clock |
U64 | Programmable clock generator | Eight channel Programmable clock generator. 4 outputs are implemented, default frequencies are 125 MHz, 21.186 MHz, 125 MHz, and 100 MHz. |
Transceiver Interfaces | ||
U16 | PCIe* x4 Golden Finger | PCIe* Gen2 x4 endpoint |
J5, J6 | SFP+ | Support 10 GE SFP+ module |
J7 | FMC | 5 Transceivers up to 12.5 Gbps |
J8 | USB Type-C | Implements USB3.1 and USB2.0 |
U26 | USB 2:1 MUX | TI HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX |
U65 | USB Redriver | TI USB1002 USB3.1 10 Gbps Dual-Channel Linear Redriver |
Memory | ||
U12, U13, U14 | DDR3 memory |
|
U4 | EPCQ-L Flash/MT25Q |
|
U58 | QSPI Flash | ISSI IS25WP256D-RHLE, 256 Mbit |
Power | ||
J12 | PCIe* ATX 2x4 | Auxiliary power supply of PCIe* system |
J13 | DC-input | 4-pin DIN power adaptor |
S14 | Power Switch | Slide switch for power input |