Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.9.2. PCIe Interface

The PCIe* x4 Gen2 Hard IP with CvP is implemented in this development kit. The position of the PCIe* channels is fixed by the hard IP. This development kit is a PCIe* add-in card. The PCIe* interface is configured to End-Point.

The PCIe* interface has the following signals:
  • Transceivers, x4, up to 5 Gbps
  • PCIE_REFCLKp/n, 100 MHz from PCIe* system
  • PCIE_SMBUS, 3.3 V level-translated to 1.8 V with U18
  • PCIE_PERSTn, 3.3 V level-translated to 1.8 V with U17
  • PCIE_WAKEn, 3.3 V level-translated to 1.8 V with U17, reserved
The PCIe* width can be selected with Jumper resistors:
  • R506 installed, x1 mode
  • R507 installed, x4 mode, this is the default mode
There are three power rails from PCIe* golden finger connector:
  • +12 V, ±8%, up to 75 W, is used as power of the board
  • +3.3 V, ±9%, up to 10 W, is not used on this board
  • +3.3 Vaux, ±9%, 375 mA max, is not used since wakeup is not supported
Level Two Title