Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide

Document Version Changes
2024.08.09
  • Updated the Overview section:
    • Added new table: Ordering Information.
    • Added new Figures: Cyclone® 10 GX FPGA Development Kit (Power Solution 2)—Top View and Cyclone® 10 GX FPGA Development Kit (Power Solution 1)—Top View.
  • Retitled the General Development Kit Description topic to Feature Summary.
  • Added new topic—Bock Diagram.
  • Merged content in Handling the Board into Recommended Operating Conditions.
  • Updated Installing the Quartus Prime Software:
    • Retitled the Installing the Quartus Prime Software topic to Quartus Prime Software and Driver Installation.
    • Merged content in Installing the Intel FPGA Download Cable Driver into Quartus Prime Software and Driver Installation.
  • Updated Board Overview:
    • Updated Figure: Cyclone® 10 GX FPGA Development Kit Block Diagram.
    • Updated Table: Board Components Table.
  • Updated Cyclone 10 GX FPGA:
    • Updated the description for C10_CS0n, C10_AS_D[0:3], and C10_DCLK in Table: Cyclone® 10 GX FPGA I/O Resources Table.
  • Updated FPGA Configuration:
    • Updated topic description.
    • Updated Figures: JTAG Topology Block Diagram and FPGA Configuration Scheme Block Diagram.
  • Updated Power:
    • Retitled the Power Distribution Scheme figure to Power Distribution Scheme for Power Solution 1.
    • Added new Figure: Power Distribution Scheme for Power Solution 2.
    • Added new Table: Power Solution 2.
  • Updated I2C/PMBUS:
    • Retitled the I2C Bus Topology figure to I2C Bus Topology for Power Solution 1.
    • Added new figure: I2C Bus Topology for Power Solution 2.
  • Updated Board Test System:
    • Updated Preparing the Board.
    • Removed Figure: About BTS.
    • Updated the following figures:
      • BTS GUI
      • The System Info Tab
      • The GPIO Tab
      • The Flash Tab
      • The XCVR Tab
      • The FMC Tab
      • The DDR3 Tab
2018.08.15

Updated LEDs. The D19, D20, D21, D22 board reference function updated to '1 to light, output from FPGA'.

2018.03.06
  • In Default Switch and Jumper Settings, updated value for S3.1 in DIP Switch Settings table to OPEN/OFF/1.
  • In Switches, in DIP Switch Settings table, updated default value of S3.1 to 1. Changed values in S3 description to 01 - Internal Oscillator. Set to 01 by default.
2017.12.18 Initial release.
Level Two Title