Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller Serial Port Registers Target Frequency (MHz) fXTAL Default Set F_vco Frequency Divider Disable Read Import
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

4.3.9. Clock Controller

The Clock Controller application sets the Si5332 programmable oscillators to any frequency between 5 MHz and 312.5 MHz differential.

The Clock Controller application sets the Si570 programmable oscillators to any frequency between 10 MHz and 725 MHz.

The Clock Control communicates with the MAX® 10 on the board through the JTAG bus. The programmable oscillator are connected to the MAX® 10 device through a 2-wire serial bus.

Figure 15. Clock Controller—Si570

Serial Port Registers

Shows the current values from the Si570 registers for frequency configuration.

Target Frequency (MHz)

Allows you to specify the frequency of the clock. Legal values are between 10 MHz and 725 MHz with eight digits of precision to the right of the decimal point. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target Frequency control works in conjunction with the Set control.

fXTAL

Shows the calculated internal fixed-frequency crystal based on the serial port register values.

Default

Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.

Set

Sets the programmable oscillator frequency for the selected clock to the value in the Target Frequency control for the programmable oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Altera recommends resetting the FPGA logic after changing frequencies.

Figure 16. Clock Controller—Si5332

Si5332 tab displays the same GUI controls for each clock generators. The Si5332 is a high-performance, low-jitter clock generator capable of synthesizing five independent banks for user-programmable clock frequencies up to 312.5 MHz.

Note: Currently, only OUT0 and OUT1 can support fractional synthesis output for this board. If you want to change the divider setting, you should use Silicon Laboratories ClockBuilder* tool to generate the register map and use import function on this application.

The controls of the clock controller are described below:

F_vco

Displays the generating signal value of the voltage-controlled oscillator.

Frequency

Allows you to specify the frequency of the clock MHz.

Divider

Display the divider mode and value currently being used on this board.

Disable

Allows you to disable a single output.

Read

Reads the current frequency setting for the oscillator.

Set

Sets the programmable oscillator frequency for the selected clock to the value in OUT0, OUT1, OUT4, OUT6 and OUT7 controls for the Si5332. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Altera recommends resetting the FPGA logic after changing frequencies.

Import

Import register map file generated from Silicon Laboratories ClockBuilder Desktop.

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