25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

7.5.1. TX Statistics Registers

Table 26.  Transmit Side Statistics Registers The TX statistics counters do not reflect TX CRC errors the user forces by asserting the l1_tx_error signal.

Address

Name-

Description

Access

0x800

CNTR_TX_FRAGMENTS_LO

Number of transmitted frames less than 64 bytes and reporting a CRC error (lower 32 bits).

RO

0x801

CNTR_TX_FRAGMENTS_HI

Number of transmitted frames less than 64 bytes and reporting a CRC error (upper 32 bits).

RO

0x802

CNTR_TX_JABBERS_LO

Number of transmitted oversized frames reporting a CRC error (lower 32 bits).

RO

0x803

CNTR_TX_JABBERS_HI

Number of transmitted oversized frames reporting a CRC error (upper 32 bits).

RO

0x804

CNTR_TX_FCS_LO

Number of transmitted packets with FCS errors. (lower 32 bits).

RO

0x805

CNTR_TX_FCS_HI

Number of transmitted packets with FCS errors. (upper 32 bits).

RO

0x806

CNTR_TX_CRCERR_LO

Number of transmitted frames with a frame of length at least 64 reporting a CRC error (lower 32 bits).

RO

0x807

CNTR_TX_CRCERR_HI

Number of transmitted frames with a frame of length at least 64 reporting a CRC error (upper 32 bits).

RO

0x808

CNTR_TX_MCAST_DATA_ERR_LO

Number of errored multicast frames transmitted, excluding control frames (lower 32 bits).

RO

0x809

CNTR_TX_MCAST_DATA_ERR_HI

Number of errored multicast frames transmitted, excluding control frames (upper 32 bits).

RO

0x80A

CNTR_TX_BCAST_DATA_ERR_LO

Number of errored broadcast frames transmitted, excluding control frames (lower 32 bits).

RO

0x80B

CNTR_TX_BCAST_DATA_ERR_HI

Number of errored broadcast frames transmitted, excluding control frames (upper 32 bits).

RO

0x80C

CNTR_TX_UCAST_DATA_ERR_LO

Number of errored unicast frames transmitted, excluding control frames (lower 32 bits).

RO

0x80D

CNTR_TX_UCAST_DATA_ERR_HI

Number of errored unicast frames transmitted, excluding control frames (upper 32 bits).

RO

0x80E

CNTR_TX_MCAST_CTRL_ERR_LO

Number of errored multicast control frames transmitted (lower 32 bits).

RO

0x80F

CNTR_TX_MCAST_CTRL_ERR_HI

Number of errored multicast control frames transmitted (upper 32 bits).

RO

0x810

CNTR_TX_BCAST_CTRL_ERR_LO

Number of errored broadcast control frames transmitted (lower 32 bits).

RO

0x811

CNTR_TX_BCAST_CTRL_ERR_HI

Number of errored broadcast control frames transmitted (upper 32 bits).

RO

0x812

CNTR_TX_UCAST_CTRL_ERR_LO

Number of errored unicast control frames transmitted (lower 32 bits).

RO

0x813

CNTR_TX_UCAST_CTRL_ERR_HI

Number of errored unicast control frames transmitted (upper 32 bits).

RO

0x814

CNTR_TX_PAUSE_ERR_LO

Number of errored pause frames transmitted (lower 32 bits).

RO

0x815

CNTR_TX_PAUSE_ERR_HI

Number of errored pause frames transmitted (upper 32 bits).

RO

0x816

CNTR_TX_64B_LO

Number of 64-byte transmitted frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes.

RO

0x817

CNTR_TX_64B_HI

Number of 64-byte transmitted frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes.

RO

0x818

CNTR_TX_65to127B_LO

Number of transmitted frames between 65–127 bytes (lower 32 bits).

RO

0x819

CNTR_TX_65to127B_HI

Number of transmitted frames between 65–127 bytes (upper 32 bits).

RO

0x81A

CNTR_TX_128to255B_LO

Number of transmitted frames between 128–255 bytes (lower 32 bits).

RO

0x81B

CNTR_TX_128to255B_HI

Number of transmitted frames between 128–255 bytes (upper 32 bits).

RO

0x81C

CNTR_TX_256to511B_LO

Number of transmitted frames between 256–511 bytes (lower 32 bits).

RO

0x81D

CNTR_TX_256to511B_HI

Number of transmitted frames between 256–511 bytes (upper 32 bits).

RO

0x81E

CNTR_TX_512to1023B_LO

Number of transmitted frames between 512–1023 bytes (lower 32 bits).

RO

0x81F

CNTR_TX_512to1023B_HI

Number of transmitted frames between 512–1023 bytes (upper 32 bits).

RO

0x820

CNTR_TX_1024to1518B_LO

Number of transmitted frames between 1024–1518 bytes (lower 32 bits).

RO

0x821

CNTR_TX_1024to1518B_HI

Number of transmitted frames between 1024–1518 bytes (upper 32 bits).

RO

0x822

CNTR_TX_1519toMAXB_LO

Number of transmitted frames of size between 1519 bytes and the number of bytes specified in the MAX_TX_SIZE_CONFIG register (lower 32 bits).

RO

0x823

CNTR_TX_1519toMAXB_HI

Number of transmitted frames of size between 1519 bytes and the number of bytes specified in the MAX_TX_SIZE_CONFIG register (upper 32 bits).

RO

0x824

CNTR_TX_OVERSIZE_LO

Number of oversized frames (frames with more bytes than the number specified in the MAX_TX_SIZE_CONFIG register) transmitted (lower 32 bits).

RO

0x825

CNTR_TX_OVERSIZE_HI

Number of oversized frames (frames with more bytes than the number specified in the MAX_TX_SIZE_CONFIG register) transmitted (upper 32 bits).

RO

0x826

CNTR_TX_MCAST_DATA_OK_LO

Number of valid multicast frames transmitted, excluding control frames (lower 32 bits).

RO

0x827

CNTR_TX_MCAST_DATA_OK_HI

Number of valid multicast frames transmitted, excluding control frames (upper 32 bits).

RO

0x828

CNTR_TX_BCAST_DATA_OK_LO

Number of valid broadcast frames transmitted, excluding control frames (lower 32 bits).

RO

0x829

CNTR_TX_BCAST_DATA_OK_HI

Number of valid broadcast frames transmitted, excluding control frames (upper 32 bits).

RO

0x82A

CNTR_TX_UCAST_DATA_OK_LO

Number of valid unicast frames transmitted, excluding control frames (lower 32 bits).

RO

0x82B

CNTR_TX_UCAST_DATA_OK_HI

Number of valid unicast frames transmitted, excluding control frames (upper 32 bits).

RO

0x82C

CNTR_TX_MCAST_CTRL_LO

Number of valid multicast frames transmitted, excluding data frames (lower 32 bits).

RO

0x82D

CNTR_TX_MCAST_CTRL_HI

Number of valid multicast frames transmitted, excluding data frames (upper 32 bits).

RO

0x82E

CNTR_TX_BCAST_CTRL_LO

Number of valid broadcast frames transmitted, excluding data frames (lower 32 bits).

RO

0x82F

CNTR_TX_BCAST_CTRL_HI

Number of valid broadcast frames transmitted, excluding data frames (upper 32 bits).

RO

0x830

CNTR_TX_UCAST_CTRL_LO

Number of valid unicast frames transmitted, excluding data frames (lower 32 bits).

RO

0x831

CNTR_TX_UCAST_CTRL_HI

Number of valid unicast frames transmitted, excluding data frames (upper 32 bits).

RO

0x832

CNTR_TX_PAUSE_LO

Number of valid pause frames transmitted (lower 32 bits).

RO

0x833

CNTR_TX_PAUSE_HI

Number of valid pause frames transmitted (upper 32 bits).

RO

0x834

CNTR_TX_RUNT_LO

Number of transmitted runt packets (lower 32 bits). The IP core does not transmit frames of length less than nine bytes. The IP core pads frames of length nine bytes to 64 bytes to extend them to 64 bytes. Therefore, this counter does not increment in normal operating conditions.

RO

0x835

CNTR_TX_RUNT_HI

Number of transmitted runt packets (upper 32 bits). The IP core does not transmit frames of length less than nine bytes. The IP core pads frames of length nine bytes to 64 bytes to extend them to 64 bytes. Therefore, this counter does not increment in normal operating conditions.

RO

0x836–0x844

Reserved

0x845

CNTR_TX_CONFIG

Bits[2:0]: Configuration of TX statistics counters:
  • Bit[2]: Shadow request (active high): When set to the value of 1, TX statistics collection is paused. The underlying counters continue to operate, but the readable values reflect a snapshot at the time the pause flag was activated. Write a 0 to release.
  • Bit[1]: Parity-error clear. When software sets this bit, the IP core clears the parity bit CNTR_TX_STATUS[0]. This bit (CNTR_TX_CONFIG[1]) is self-clearing.
  • Bit[0]: Software can set this bit to the value of 1 to reset all of the TX statistics registers at the same time. This bit is self-clearing.
Bits[31:3] are Reserved. 		RW
0x846 CNTR_TX_STATUS
  • Bit[1]: Indicates that the TX statistics registers are paused (while CNTR_TX_CONFIG[2] is asserted).
  • Bit[0]: Indicates the presence of at least one parity error in the TX statistics counters.
Bits[31:2] are Reserved. 		RO
0x847–0x85F

Reserved
0x860 TxPayloadOctetsOK_LO Number of transmitted payload bytes in frames with no FCS, undersized, oversized, or payload length errors. If VLAN detection is turned off for the TX MAC (bit[1] of the TX_MAC_CONTROL register at offset 0x40A has the value of 1), the IP core counts the VLAN header bytes (4 bytes for VLAN and 8 bytes for stacked VLAN) as payload bytes. This register is compliant with the requirements for a OctetsTransmittedOK in section 5.2.2.1.8 of the IEEE Standard 802.3-2008. RO
0x861 TxPayloadOctetsOK_HI RO
0x862 TxFrameOctetsOK_LO Number of transmitted bytes in frames with no FCS, undersized, oversized, or payload length errors. This register is compliant with the requirements for ifOutOctets in RFC3635 (Managed Objects for Ethernet-like Interface Types) and TX etherStatsOctets in RFC2819(Remote Network Monitoring Management Information Base (RMON)). RO
0x863 TxFrameOctetsOK_HI RO
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