25G Ethernet Arria® 10 FPGA IP User Guide

ID 683639
Date 7/25/2024
Public
Document Table of Contents

6.3. Transceivers

The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. In many cases, the same ATX PLL can serve as input to an additional transceiver that has similar input clocking requirements. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
Table 14.  Transceiver Signals

Signal

Direction

Description

tx_serial Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz .
tx_serial_clk Input High speed serial clock driven by the ATX PLL. The frequency of this clock is 12.890625 GHz.
tx_pll_locked Input Lock signal from ATX PLL. Indicates all ATX PLL(s) are locked.