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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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6.4. Transceiver Reconfiguration Signals
You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® memory-mapped interface.
The Avalon® memory-mapped interface implements a standard memory-mapped protocol. You can connect an Avalon® master to this bus to access the registers of the embedded Transceiver PHY IP core.
Port Name | Direction | Description |
---|---|---|
reconfig_clk | Input | Avalon® clock. The clock frequency is 100-125 MHz. All signals transceiver reconfiguration interface signals are synchronous to reconfig_clk . |
reconfig_reset | Input | Resets the Avalon® memory-mapped interface and all of the registers to which it provides access. |
reconfig_write | Input | Write enable signal. Signal is active high. |
reconfig_read | Input | Read enable signal. Signal is active high. |
reconfig_address[10 :0] | Input | Address bus. |
reconfig_writedata[31:0] | Input | A 32-bit data write bus. reconfig_address specifies the address. |
reconfig_readdata[31:0] | Output | A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted. |
reconfig_waitrequest | Output | Indicates the Avalon® memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted. |
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