25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.25 23.3 20.1.0 Removed references to NCSim simulator.
2021.03.29 21.1 19.4.0 Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
  • tx_etstamp_ins_ctrl_residence_time_calc_format
  • tx_egress_timestamp_64b_data[63:0]
  • tx_egress_timestamp_96b_fingerprint[(W–1):0]
  • tx_egress_timestamp_64b_fingerprint[(W–1):0]
2020.10.12 20.3 19.4.0
  • Updated the description in the About the 25G Ethernet Intel FPGA IP section.
  • Updated the description in the 25G Ethernet Intel FPGA IP Supported Features section.25G Ethernet Intel FPGA IP Supported Features
  • Added a note to the Length Checking section to state that the MAC has a counter limit of 0xFFFF starting from Quartus® Prime Pro Edition software version 20.3 onward.
  • Made minor editorial updates throughout the document.
2020.06.22 19.4 19.4.0
  • Updated the Length/Type Field Processing section.
  • Update the descriptions to the following signals in Table: Avalon® Streaming TX Datapath:
    • l1_tx_data[63:0]
    • l1_tx_valid
    • l1_tx_ready
  • Removed Figure: Client to 25G Ethernet Intel FPGA IP MAC Avalon Streaming Interface.
  • Added the following Figures:
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (1 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (2 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (1 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (2 of 2)
2020.04.13 19.4 19.4.0
  • Updated the Simulating the IP Core section.
  • Updated the Length Checking section.
  • Updated Table: Avalon® Streaming RX Datapath to update the description for l1_rx_error[5:0].
  • Updated Table: Receive Side Statistics Registers to update the descriptions for CNTR_RX_1519toMAXB_HI, CNTR_RX_OVERSIZE_LO, and CNTR_RX_OVERSIZE_HI.
  • Updated the description and reset value for RXMAC_CONTROL and description for LINK_FAULT in Table: RX MAC Registers.
2020.02.20 19.4 19.4.0
  • Updated the description for frame monitoring and statistics in the 25G Ethernet Intel FPGA IP Core Supported Features section.
  • Updated the Debugging the Link section.
2019.12.16 19.4 19.4.0
  • Updated the description in the About the 25G Ethernet Intel FPGA IP Core section.
  • Updated Table: IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core for Arria® 10 Devices.
  • Updated the description in the PTP Transmit Functionality section.
  • Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
    • tx_etstamp_ins_ctrl_offset_timestamp[15:0]
    • tx_etstamp_ins_ctrl_offset_correction_field[15:0]
    • tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
    • tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
  • Added rx_am_lock to Table: Miscellaneous Status and Debug Signals.
  • Updated the description and reset value for RXMAC_CONTROL in Table: RX MAC Registers.
  • Updated the description of the Avalon® Memory-Mapped Management Interface section.
  • Updated the Statistics Registers section.
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Updated for latest Intel® branding standards.
2018.10.23 17.0 17.0
  • Updated Table: PHY Registers:
    • Added bit[1] description for RX_PCS_FULLY_ALIGNED_S.
    • Updated the descriptions for KHZ_REF, KHZ_RX, and KHZ_TX.
  • Made minor editorial updates to the document.
2018.07.17 17.0 17.0
  • Renamed the document as 25G Ethernet Intel Arria 10 FPGA IP User Guide.
  • Renamed "25G Ethernet" IP core to "25G Ethernet Intel FPGA IP" as per Intel rebranding.
  • Updated Table: TX 1588 PTP Registers to correct the HW reset value of the TX_PTP_CLK_Period register to 0x28F5C.
  • Updated Table: RX 1588 PTP Registers to correct the HW reset value of the RX_PTP_CLK_Period register to 0x28F5C.
  • Updated for latest Intel branding standards.
Date Quartus Prime Version Changes
2017.11.07 17.0

Added link to KDB Answer that provides workaround for potential jitter on Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Handling Potential Jitter in Arria 10 Devices .

2017.08.28 17.0
2016.10.31 16.1 Initial release.
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