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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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4.1.5.1. RX RSFEC
If you turn on Enable RS-FEC in the 25G Ethernet Intel FPGA IP parameter editor, the IP core includes Reed-Solomon forward error correction (FEC) in both the receive and transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 108 of the IEEE Standard 802.3by. The Reed-Solomon FEC algorithm includes the following modules:
- Alignment marker lock
- 66:80 gearbox
- High-speed Reed-Solomon decoder
- 80:257 gearbox
- 256B/257B to 64B/66B Transcoding
You cannot turn on both Enable RS-FEC and Enable IEEE 1588 in the 25G Ethernet Intel FPGA IP parameter editor.