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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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8.1. Error Insertion Test and Debugging
Error insertion allows you to test 25G Ethernet Intel FPGA IP core test error handling.
To use this feature, the Avalon® streaming TX client asserts l1_tx_error in the same cycle as l1_tx_endofpacket . The error appears as a 66-bit error block that consists of eight /E/ characters (EBLOCK_T) in the Ethernet frame. The 25G Ethernet Intel FPGA IP core overwrites Ethernet frame data with an EBLOCK_T error block when it transmits the Ethernet frame that corresponds to the packet EOP. The RX interface detects the frame corruption resulting in a CRC error output.