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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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2.6. Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® FPGA with the Programmer and verify the design in hardware.
Note: The 25G Ethernet Intel FPGA IP core design example synthesis directories include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.
Note: For additional .sdc file requirements, refer to the KDB link: How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?.