25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

7.5. Statistics Registers

The 25G Ethernet Intel FPGA IP statistics registers count Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:

  • Size of the destination address
  • Size of the source address
  • Size of the data
  • Four bytes of CRC

The statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Enable MAC statistics counters parameter in the 25G Ethernet Intel FPGA IP parameter editor, the counters are implemented in the CSR. When you turn off the Enable MAC statistics counters parameter in the 25G Ethernet Intel FPGA IP parameter editor, the counters are not implemented in the CSR, and read access to the counters returns undefined results.

After system power-up, the statistics counters have random values. You must clear these registers and confirm the system is stable before using their values. To clear the registers, use any of the following methods:

  1. Assert csr_rst_n to clear both the TX and RX statistic counters.
  2. Assert tx_rst_n to clear the TX statistic counters.
  3. Assert rx_rst_n to clear the RX statistic counters.
  4. Write 1'b1 to bit[0], eio_sys_rst of the PHY_CONFIG (0x310) register to clear both the TX and RX statistic counters.
  5. Write 1'b1 to bit[1], soft_txp_rst of the PHY_CONFIG (0x310) register to clear the TX statistic counters.
  6. Write 1'b1 to bit[2], soft_rxp_rst of the PHY_CONFIG (0x310) register to clear the RX statistic counters.
  7. Write 1'b1 to bit[0] of the CNTR_TX_CONFIG (0x845) to clear the TX statistic counters.
  8. Write 1'b1 to bit[0] of the CNTR_RX_CONFIG (0x945) to clear the RX statistic counters.

The configuration register at offset 0x845 allows you to clear all of the TX statistics counters. The configuration register at offset 0x945 allows you to clear all of the RX statistics counters. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.

Reading the value of a statistics register does not affect its value.

To ensure that the counters you read are consistent, you should issue a shadow request to create a snapshot of all of the TX or RX statistics registers, by setting bit [2] of the configuration register at offset 0x845 or 0x945, respectively. Until you reset this bit, the counters continue to increment but the readable values remain constant. You can read bit [1] of the status register at offset 0x846 or 0x946, respectively, to confirm your shadow request has been granted or released.


Section Content
TX Statistics Registers
RX Statistics Registers

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