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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath
The RX MAC receives Ethernet frames and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes. The RX MAC processes all incoming valid frames.
Figure 12. Flow of Client Frame With Preamble Pass-Through Turned On This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).
Figure 13. Flow of Client Frame With Preamble Pass-Through Turned Off This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).
Figure 14. RX MAC Datapath