25G Ethernet Arria® 10 FPGA IP User Guide

ID 683639
Date 7/25/2024
Public
Document Table of Contents

1.5. Performance and Resource Utilization

The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 100. The timing margin for this IP core is a minimum of 15%.

Table 5.  IP Core Variation Encoding for Resource Utilization Table"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C
Parameter
Read Latency 0 0 3
Enable RS-FEC On
Enable flow control Standard flow control, 1 queue Standard flow control, 1 queue
Enable link fault generation On
Enable preamble passthrough On
Enable TX CRC passthrough On
Enable MAC statistics counters On On
Enable IEEE 1588 On
Table 6.  IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core for Arria® 10 DevicesLists the resources and expected performance for selected variations of the 25G Ethernet Intel FPGA IP core.

These results were obtained using the Quartus® Prime software v19.4.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus® Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

M20K Memory Blocks

A 3100 7200 0
B 13300 30100 19
C 11400 25300 32