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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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1.5. Performance and Resource Utilization
The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 100. The timing margin for this IP core is a minimum of 15%.
IP Core Variation | A | B | C |
---|---|---|---|
Parameter | |||
Read Latency | 0 | 0 | 3 |
Enable RS-FEC | — | On | — |
Enable flow control | — | Standard flow control, 1 queue | Standard flow control, 1 queue |
Enable link fault generation | — | — | On |
Enable preamble passthrough | — | — | On |
Enable TX CRC passthrough | On | — | — |
Enable MAC statistics counters | — | On | On |
Enable IEEE 1588 | — | — | On |
IP Core Variation |
ALMs |
Dedicated Logic Registers |
M20K Memory Blocks |
---|---|---|---|
A | 3100 | 7200 | 0 |
B | 13300 | 30100 | 19 |
C | 11400 | 25300 | 32 |