25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

3. 25G Ethernet Intel FPGA IP Parameters

The 25G Ethernet Intel FPGA IP parameter editor provides the parameters you can set to configure the 25G Ethernet Intel FPGA IP core and simulation testbenches.

The 25G Ethernet Intel FPGA IP parameter editor includes an Example Design tab. For information about that tab, refer to the 25G Ethernet Design Example User Guide .

Table 10.  IP Core Parameters
Parameter Range Default Setting Description
General Options
Device Family Arria 10 Arria 10 Selects the device family.
Ready Latency 0, 3 0

Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l1_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon® Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the datapath.

If you set the readyLatency to 3 and turn on standard flow control, data might be delayed in the IP core while the IP core is backpressured.

PCS/PMA Options
Enable RS-FEC Enabled, Disabled Disabled When enabled, the IP core implements Reed-Solomon forward error correction (FEC).

This parameter is not available if you turn on Enable IEEE 1588 .

Flow Control Options
Enable flow control Enabled, Disabled Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames. Register settings control flow control behavior, including whether the IP core implements standard flow control or priority-based flow control.

If you turn on standard flow control and set the readyLatency to 3, data might be delayed in the IP core while the IP core is backpressured.

Number of queues 1-8 8 Specifies the number of queues used in managing flow control.
MAC Options
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Standard for Ethernet. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable TX CRC passthrough Enabled, Disabled Disabled When enabled, TX MAC does not insert the CRC-32 checksum in the out-going frame. In pass-through mode, the client must provide frames with at least 64 bytes, including the Frame Check Sequence (FCS). When disabled, the TX MAC computes and inserts a 32-bit FCS in the TX MAC frame.

This parameter is not available if you turn on Enable IEEE 1588 .

Enable MAC statistics counters Enabled, Disabled Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic.
IEEE 1588 Options
Enable IEEE 1588 Enabled, Disabled Disabled If enabled, the IP core supports the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol, by providing the hooks to implement the Precise Timing Protocol (PTP).

This parameter is not available if you turn on Enable TX CRC passthrough.

This parameter is not available if you turn on Enable RS-FEC .

Time of day format Enable 96-bit timestamp format, Enable 64-bit timestamp format, Enable both formats Enable both formats Specifies the interface to the Time of Day module. If you select Enable both formats, the IP core includes both the 64-bit interface and the 96-bit interface.

This parameter is available only in variations with Enable IEEE 1588 turned on. The IP core provides the Time of Day interface; the IP core does not include Time of Day and synchronizer modules to connect to this interface.

Fingerprint width 1–32 4 Specifies the number of bits in the fingerprint that the IP core handles.

This parameter is available only in variations with Enable IEEE 1588 turned on.

Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint (NPDME) Enabled, Disabled Disabled

If enabled, the IP core turns on the following features in the Arria® 10 PHY IP core that is included in the 25G Ethernet Intel FPGA IP core:

  • Enable Native PHY Debug Master Endpoint (NPDME)
  • Enable capability registers

If turned off, the IP core is configured without these features.

For information about these Arria® 10 features, refer to the Arria® 10 Transceiver PHY User Guide. .

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