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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
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1.4.2. Compilation Checking
Altera performs compilation testing on an extensive set of 25G Ethernet Intel FPGA IP core variations and designs to ensure the Quartus® Prime software places and routes the IP core ports correctly.