25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

6.6. 1588 PTP Interface Signals

Table 17.  Signals of the 1588 Precision Time Protocol InterfaceSignals are clocked by clk_rxmac or clk_txmac, as specified. All 64-bit output signals are in the Altera 64-bit TOD format, and you are expected to drive all 64-bit input signals in this format.

Signal Name

Direction

Description

PTP Interface to TOD module
tx_time_of_day_96b_data[95:0] Input Current V2-format (96-bit) TOD in clk_txmac clock domain. Connect this signal to the external TOD module.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

tx_time_of_day_64b_data[63:0] Input Current 64-bit TOD in clk_txmac clock domain. Connect this signal to the external TOD module.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

rx_time_of_day_96b_data[95:0] Input Current V2-format (96-bit) TOD in clk_rxmac clock domain. Connect this signal to the external TOD module.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

rx_time_of_day_64b_data[63:0] Input Current 64-bit TOD in clk_rxmac clock domain. Connect this signal to the external TOD module.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

PTP Interface to Client
TX Signals Related to One Step Processing
tx_etstamp_ins_ctrl_timestamp_insert Input Indicates the current packet on the TX client interface is a 1588 PTP packet, and directs the IP core to process the packet in one-step processing insertion mode. In this mode, the IP core overwrites the timestamp of the packet with the timestamp field when the packet appears on the TX Ethernet link.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

If the TX client asserts this signal simultaneously with tx_etstamp_ins_ctrl_residence_time_update , the results are undefined.

tx_etstamp_ins_ctrl_residence_time_update Input Indicates the current packet on the TX client interface is a 1588 PTP packet, and directs the IP core to process the packet in one-step processing correction mode. In this mode, the IP core adds the latency through the IP core (residence time) to the current contents of the timestamp field.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

If the TX client asserts this signal simultaneously with either of tx_etstamp_ins_ctrl_timestamp_insert or tx_egress_timestamp_request_valid, the results are undefined.

tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] Input

Indicates the V2-format TOD when the packet entered the system.

The TX client must ensure this signal is valid in each TX SOP cycle when it asserts tx_etstamp_ins_ctrl_residence_time_update. The TX client must maintain the desired value on this signal while the TX SOP signal is asserted. This signal is useful only in transparent clock mode when the TX client asserts tx_etstamp_ins_ctrl_residence_time_update.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] Input

Indicates the TOD (in Altera 64-bit format) when the packet entered the system.

The TX client must ensure this signal is valid in each TX SOP cycle when it asserts tx_etstamp_ins_ctrl_residence_time_update. The TX client must maintain the desired value on this signal while the TX SOP signal is asserted. This signal is useful only in transparent clock mode when the TX client asserts tx_etstamp_ins_ctrl_residence_time_update.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

tx_etstamp_ins_ctrl_timestamp_format Input Specifies the timestamp format (V1 or V2 format) for the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert. Values are:
  • 1'b0: 96-bit timestamp format (V2)
  • 1'b1: 64-bit timestamp format (V1)

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

If the client specifies the V1 format, you read and write the V1 format TOD (32 bits of seconds and 32 bits of nanoseconds) in bits [79:16] of the 96-bit timestamp and TOD signals.

Note: If you set the Time of day format parameter to the value of Enable 64-bit timestamp format, the results of asserting tx_etstamp_ins_ctrl_timestamp_insert are undefined. Therefore, the timestamp in any case maps to the 96-bit signals.
tx_etstamp_ins_ctrl_residence_time_calc_format Input Specifies the TOD format (64-bit TOD format or the V2 96-bit TOD format) for the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_residence_time_update. Values are:
  • 1'b0: 96-bit TOD format (V2)
  • 1'b1: 64-bit TOD format (48-bit ns and 16-bit fns)

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

If you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats, and the client specifies the 64-bit TOD format, the IP core uses the 64-bit TOD format for residence time calculation.

If you set the Time of day format parameter to the value of Enable 64-bit timestamp format and the client specifies the 96-bit format (V2), the results are undefined.

tx_etstamp_ins_ctrl_offset_timestamp[15:0]

Input

Specifies the byte offset of the timestamp information in the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert. The IP core overwrites the value at this offset. The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

If the packet supports V2 format, the timestamp has 96 bits. In this case, the IP core inserts ten bytes (bits [95:16]) of the timestamp at this offset and the remaining two bytes (bits [15:0]) of the timestamp at the offset specified in tx_etstamp_ins_ctrl_offset_correction_field.

The TX client must ensure that:

  • The offset includes the entire timestamp in a single packet.
  • If the packet is more than 256 bytes, the offset supports inclusion of the entire timestamp in the first 256 bytes of the packet.
  • The timestamp bytes do not overlap with the bytes in any other field, including the UDP checksum field. (If these particular two fields overlap, the result is undefined).
tx_etstamp_ins_ctrl_offset_correction_field[15:0] Input If the TX client simultaneously asserts tx_etstamp_ins_ctrl_residence_time_update, this signal specifies the byte offset of the correction field in the current packet.

If the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert and deasserts (sets to the value of 0) the tx_etstamp_ins_ctrl_timestamp_format signal, this signal specifies the byte offset of bits [15:0]] of the timestamp.

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

In addition, the TX client must ensure that:

  • The offset includes the entire correction field or timestamp in a single packet.
  • If the packet is more than 256 bytes, the offset supports inclusion of the entire timestamp or correction field in the first 256 bytes of the packet.
  • The correction field or timestamp bytes do not overlap with the bytes in any other field, including the UDP checksum field. (If these particular two fields overlap, the result is undefined).
tx_etstamp_ins_ctrl_checksum_zero Input The TX client asserts this signal during a TX SOP cycle to tell the IP core to zero the UDP checksum in the current packet.

If the TX client asserts the tx_etstamp_ins_ctrl_checksum_correct signal, it cannot assert this signal. This signal is meaningful only in one-step clock mode.

A zeroed UDP checksum indicates the checksum value is not necessarily correct. This information is useful to tell the application to skip checksum checking of UDP IPv4 packets. This function is illegal for UDP IPv6 packets.

tx_etstamp_ins_ctrl_offset_checksum_field[15:0] Input Indicates the byte offset of the UDP checksum in the current packet. The TX client must ensure this signal has a valid value during each TX SOP cycle when it also asserts the tx_etstamp_ins_ctrl_checksum_zero signal. Holds the byte offset of the two bytes in the packet that the IP core should reset. This signal is meaningful only in one-step clock mode.

The TX client must ensure that:

  • The offset includes the entire checksum in a single packet.
  • The checksum bytes do not overlap with the bytes in any other field, including the timestamp bytes. (If these particular two fields overlap, the result is undefined).
tx_etstamp_ins_ctrl_checksum_correct Input The TX client asserts this signal during a TX SOP cycle to tell the IP core to update (correct) the UDP checksum in the current packet.

If the TX client asserts the tx_etstamp_ins_ctrl_checksum_zero signal, it cannot assert this signal. This signal is meaningful only in one-step clock mode.

The application must assert this signal for correct processing of UDP IPv6 packets.
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] Input Indicates the byte offset of the UDP checksum correction field in the current packet represented by the extended bytes before CRC. The TX client must ensure this signal has a valid value during each TX SOP cycle when it also asserts the tx_etstamp_ins_ctrl_checksum_correct signal. Holds the byte offset of the two bytes in the packet that the IP core should correct. This signal is meaningful only in one-step clock mode.

The TX client must ensure that:

  • The offset and length of the checksum correction field includes the entire two bytes of the checksum correction field in a single packet.
  • The checksum bytes do not overlap with the bytes in any other field, including the timestamp bytes. (If these particular two fields overlap, the result is undefined).
  • The end of the UDP payload of the PTP packet is extended by 2 bytes. The MAC function modifies the extended bytes to ensure that the UDP checksum remains uncompromised.
tx_egress_asymmetry_update Input Indicates the IP core should include the value in the TX_PTP_ASYM_DELAY register in its correction calculations. The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

This option is useful in one-step correction mode.
TX Signals Related to Two Step Processing
tx_egress_timestamp_request_valid Input Indicates the current packet on the TX client interface is a 1588 PTP packet, and directs the IP core to process the packet in two-step processing mode. In this mode, the IP core outputs the timestamp of the packet when it exits the IP core, and does not modify the packet timestamp information.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

If the TX client asserts this signal simultaneously with tx_etstamp_ins_ctrl_residence_time_update, the results are undefined.

tx_egress_timestamp_96b_data[95:0]

Output

Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_96b_valid signal is asserted. This signal is meaningful only in two-step clock mode.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

tx_egress_timestamp_96b_valid Output Indicates that the tx_egress_timestamp_96b_data and tx_egress_timestamp_96b_fingerprint signals are valid in the current clk_txmac clock cycle. This signal is meaningful only in two-step clock mode.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

tx_egress_timestamp_64b_data[63:0]

Output

Provides the timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_64b_valid signal is asserted. This signal is meaningful only in two-step clock mode.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

tx_egress_timestamp_64b_valid Output Indicates that the tx_egress_timestamp_64b_data and tx_egress_timestamp_64b_fingerprint signals are valid in the current clk_txmac clock cycle. This signal is meaningful only in two-step clock mode.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

tx_egress_timestamp_request_fingerprint[(W–1):0]

where W is the value between 1 and 32, inclusive, that you specify for the Fingerprint width parameter

Input Fingerprint of the current packet.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.
tx_egress_timestamp_96b_fingerprint[(W–1):0]

where W is the value between 1 and 32, inclusive, that you specify for the Fingerprint width parameter

Output Provides the fingerprint of the 1588 PTP frame currently beginning transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_96b_valid signal is asserted.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

tx_egress_timestamp_64b_fingerprint[(W–1):0]

where W is the value between 1 and 32, inclusive, that you specify for the Fingerprint width parameter

Output Provides the fingerprint of the 1588 PTP frame currently beginning transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_64b_valid signal is asserted.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

RX Signals
rx_ingress_timestamp_96b_data[95:0]

Output

Whether or not the current packet on the RX client interface is a 1588 PTP packet, indicates the V2-format timestamp when the IP core received the packet on the Ethernet link. The IP core provides a valid value on this signal in the same cycle it asserts the RX SOP signal for 1588 PTP packets.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

rx_ingress_timestamp_96b_valid

Output

Indicates that the rx_ingress_timestamp_96b_data signal is valid in the current cycle. This signal is redundant with the RX SOP signal for 1588 PTP packets.

This signal is available only if you set the Time of day format parameter to the value of Enable 96-bit timestamp format or Enable both formats.

rx_ingress_timestamp_64b_data[63:0]

Output

Whether or not the current packet on the RX client interface is a 1588 PTP packet, indicates the 64-bit TOD (in Altera 64-bit format) when the IP core received the packet on the Ethernet link. The IP core provides a valid value on this signal in the same cycle it asserts the RX SOP signal for 1588 PTP packets.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

rx_ingress_timestamp_64b_valid

Output

Indicates that the rx_ingress_timestamp_64b_data signal is valid in the current cycle. This signal is redundant with the RX SOP signal for 1588 PTP packets.

This signal is available only if you set the Time of day format parameter to the value of Enable 64-bit timestamp format or Enable both formats.

Related Information
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