25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

6.1. TX MAC Interface to User Logic

The TX MAC provides an Avalon® streaming interface to the FPGA fabric. The minimum packet size is nine bytes.
Table 12.   Avalon® Streaming TX DatapathAll interface signals are clocked by the clk_txmac clock. The value you specify for Ready Latency in the 25G Ethernet Intel FPGA IP parameter editor is the Avalon® streaming readyLatency value on this interface.

Signal

Direction

Description

clk_txmac Output Clock for the TX logic. Derived from pll_refclk, and is an output from the 25G Ethernet Intel FPGA IP core. clk_txmac is guaranteed to be stable when tx_lanes_stable is asserted. The frequency of this clock is 390.625 MHz. All TX MAC interface signals are synchronous to clk_txmac .
l1_tx_data[63:0] Input

Data input to MAC. Bit 63 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.

The 25G Ethernet Intel FPGA IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

You must send each TX data packet without intermediate idle cycles. Therefore, you must ensure your application can provide the data for a single packet in consecutive clock cycles. If data might not be available otherwise, you must buffer the data in your design and wait to assert l1_tx_startofpacket when you are assured the packet data to send on l1_tx_data[63:0] is available or will be available on time.

If readyLatency = 0, ensure that no data transition at the l1_tx_data bus at the same clock cycle l1_tx_ready is deasserted. You can transition the data at the l1_tx_data bus at the same clock cycle l1_tx_ready is asserted.

If readyLatency = 3, ensure that no data transition at the l1_tx_data bus at the third clock cycle after l1_tx_ready is deasserted. You can transition the data at the l1_tx_data bus at the third clock cycles after l1_tx_ready is asserted.

l1_tx_valid Input When asserted, indicates valid data is available on l1_tx_data[63:0]. You must assert this signal continuously between the assertions of l1_tx_startofpacket and l1_tx_endofpacket for the same packet regardless of the l1_tx_ready status.
l1_tx_startofpacket Input When asserted, indicates the first byte of a frame. When l1_tx_startofpacket is asserted, the MSB of l1_tx_data drives the start of packet.

Packets that drive l1_tx_startofpacket and l1_tx_endofpacket in the same cycle are ignored.

l1_tx_endofpacket Input When asserted, indicates the end of a packet.

Packets that drive l1_tx_startofpacket and l1_tx_endofpacket in the same cycle are ignored.

l1_tx_empty[2:0] Input Specifies the number of empty bytes on l1_tx_data when l1_tx_endofpacket is asserted.
l1_tx_error Input

When asserted in the same cycle as l1_tx_endofpacket, indicates the current packet should be treated as an error packet. Assertion at any other position in the packet is ignored.

The TX statistics counters do not reflect errors the IP core creates in response to this signal.
l1_tx_ready Output When asserted, indicates that the MAC can accept the data. When the readyLatency = 0, the IP core accepts valid data in the same clock cycle in which it asserts l1_tx_ready. When the readyLatency = 3, the IP core accepts valid data 3 clock cycles after it asserts l1_tx_ready.
l1_txstatus_valid Output When asserted, indicates that l1_txstatus_data[39:0] is driving valid data.
l1_txstatus_data[39:0] Output

Specifies information about the transmit frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
l1_txstatus_error[6:0] Output Specifies the error type in the transmit frame. The following fields are defined:
  • Bits[6:3]: Reserved
  • Bit[2]: Payload length error
  • Bit[1]: Oversized frame
  • Bit[0]: Reserved
pause_insert_tx0[FCQN-1:0]

pause_insert_tx1[FCQN-1:0]

Input

Available if you specify Pause or PFC. Indicates to the MAC if an XON, XOFF, Pause or PFC frame should be sent. FCQN equals 1 for Pause and 1-8 for PFC.

In 1-bit programming mode, the IP core ignores pause_insert_tx1[FCQN-1:0]. In 2-bit programming mode, the higher-order bit is in pause_insert_tx1[FCQN-1:0] and the lower-order bit is in pause_insert_tx0[FCQN-1:0].

The following encodings are defined for 1-bit programming mode:

  • 0 = No request
  • 0 to 1 = Generate XOFF request
  • 1 = Continue to generate XOFF request
  • 1 to 0 = Generate XON request

The following encodings are defined for the 2-bit programming model:

  • 2'b00: No further XON/XOFF request. If there is a XON/XOFF flow control frame in progress, it is sent
  • 2'b01: Generate XON flow control frame
  • 2'b10: Generate XOFF request
  • 2'b11: Invalid
Figure 28. Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (1 of 2)This timing diagram shows l1_tx_ready asserts before l1_tx_valid asserts. TX MAC captures data at l1_tx_data bus at the same clock cycle as l1_tx_valid asserts.
Figure 29. Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (2 of 2)This timing diagram shows l1_tx_valid asserts before l1_tx_ready asserts. TX MAC captures data at l1_tx_data bus at the same clock cycle as l1_tx_ready asserts.
Figure 30. Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (1 of 2)This timing diagram shows l1_tx_ready asserts before l1_tx_valid asserts. TX MAC captures data at l1_tx_data bus at the same clock cycle as l1_tx_valid asserts.
Figure 31. Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (2 of 2)
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