25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats V2 Format V1 Format Altera 64-Bit TOD Format
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

4.1.7.5. PTP Timestamp and TOD Formats

The 25G Ethernet Intel FPGA IP core supports a 96-bit timestamp (V2 format) or a 64-bit timestamp (correction-field format) in PTP packets. The 64-bit timestamp and TOD signals of the IP core are in an Altera-defined 64-bit format that is distinct from the V1 format, for improved efficiency in one-step processing correction mode. Therefore, if your system need not handle any packets in one-step processing correction mode, you should set the Time of day format parameter to the value of Enable 96-bit timestamp format .

You control the format or formats the IP core supports with the Time of day format parameter. If you set the value of this parameter to Enable 96-bit timestamp format or Enable both formats , your IP core can support two-step processing mode, one-step processing insertion mode, and one-step processing correction mode, and can support both V1 and V2 formats. You can set the parameter value to Enable 64-bit timestamp format to support one-step processing correction mode more efficiently. However, if you do so, your IP core variation cannot support two-step processing mode and cannot support one-step processing insertion mode. If you turn on both of these parameters, the value you drive on the tx_estamp_ins_ctrl_timestamp_format or tx_etstamp_ins_ctrl_residence_time_calc_format signal determines the format the IP core supports for the current packet.

The IP core completes all internal processing in the V2 format. However, if you specify V1 format for a particular PTP packet in one-step insertion mode, the IP core inserts the appropriate V1-format timestamp in the outgoing packet on the Ethernet link.

V2 Format

The IP core maintains the time-of-day (TOD) in V2 format according to the IEEE specification:

  • Bits [95:48]: Seconds (48 bits).
  • Bits [47:16]: Nanoseconds (32 bits). This field overflows at 1 billion.
  • Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it overflows at 0xFFFF.

The IP core can receive time-of-day information from the TOD module in V2 format or in 64-bit TOD format, or both, depending on your setting for the Time of day format parameter.

V1 Format

V1 timestamp format is specified in the IEEE specification:

  • Bits [63:32]: Seconds (32 bits).
  • Bits [31:0]: Nanoseconds (32 bits). This field overflows at 1 billion.

Altera 64-Bit TOD Format

The Altera 64-bit TOD format is distinct from the V1 format and supports a longer time delay. It is intended for use in transparent clock systems, in which each node adds its own residence time to a running total latency through the system. This format matches the format of the correction field in the packet, as used in transparent clock mode.

  • Bits [63:16]: Nanoseconds (48 bits). This field can specify a value greater than 4 seconds.
  • Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it overflows at 0xFFFF.

The TOD module provides 64-bit TOD information to the IP core in this 64-bit TOD format. The expected format of all 64-bit input timestamp and TOD signals to the IP core is the Altera 64-bit TOD format. The format of all 64-bit output timestamp and TOD signals from the IP core is the Altera 64-bit TOD format. If you build your own TOD module that provides 64-bit TOD information to the IP core, you must ensure it provides TOD information in the Altera 64-bit TOD format.

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