25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface Local Fault (LF) Remote Fault (RF) Link Status Signals 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

4.1.4. Link Fault Signaling Interface

Link fault signaling reflects the health of the link. It operates between the remote Ethernet device Reconciliation Sublayer (RS) and the local Ethernet device RS. The link fault modules communicate status during the interframe period.

You enable link fault signaling by turning on Enable link fault generation in the parameter editor. For bidirectional fault signaling, the IP core implements the functionality defined in the IEEE 802.3ba 10G Ethernet Standard and Clause 46 based on the LINK_FAULT configuration register settings.

For unidirectional fault signaling, the core implements Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
Figure 15. Link Fault Block Diagram

Local Fault (LF)

If an Ethernet PHY sublayer detects a fault that makes the link unreliable, it notifies the RS of the local fault condition. If unidirectional is not enabled, the core follows Clause 46. The RS stops sending MAC data, and continuously generates a remote fault status on the TX datapath. After a local fault is detected, the RX PCS modifies the MII data and control to send local fault sequence ordered sets. Refer to Link Fault Signaling Based On Configuration and Status below.

The RX PCS cannot recognize the link fault under the following conditions:

  • The RX PCS is not fully aligned.
  • The bit error rate (BER) is high.

Remote Fault (RF)

If unidirectional is not enabled, the core follows Clause 46. If the RS receives a remote fault status, the TX datapath stops sending MAC data and continuously generates idle control characters. If the RS stops receiving fault status messages, it returns to normal operation, sending MAC client data. Refer to Link Fault Signaling Based On Configuration and Status below.

Link Status Signals

The MAC RX generates two link fault signals: local_fault_status and remote_fault_status.
Note: These signals are real time status signals that reflect the status of the link regardless of the settings in the link fault configuration register.
This register is generated only if you turn on Enable link fault generation . The MAC TX interface uses the link fault status signals for additional link fault signaling.
Table 11.  Link Fault Signaling Based On Configuration and StatusFor more information about the LINK_FAULT register, refer to TX MAC Registers.
LINK_FAULT Register (0x405) Real Time Link Status Configured TX Behavior Comment
Bit [0] Bit [3] Bit [1] Bit [2]

LF Received

RF Received

TX Data

TX RF

1'b0 Don't care Don't care Don't care Don’t care Don’t care On Off

Disable Link fault signaling on TX.

RX still reports link status.

TX side Link fault signaling disabled on the link.

TX data and idle.
1'b1 1'b1 Don't care Don't care Don't care Don't care Off On

Force RF.

TX: Stop data. Transmit RF only
1'b1 1'b0 1'b1 1'b1 Don't care Don't care On Off

Unidir: Backwards compatible.

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 On On

Unidir: LF received.

TX: Transmit data 1 column IDLE after end of packet and RF

1'b1 1'b0 1'b1 1'b0 1'b0 1'b1 On Off

Unidir: RF receives

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b1 1'b0 1'b0 1'b0 On Off

Unidir: No link fault

TX: Transmit data and idle. No RF.
1'b1 1'b0 1'b0 Don't care 1'b1 1'b0 Off On

Bidir: LF received

TX: Stop data. Transmit RF only.
1'b1 1'b0 1'b0 Don't care 1'b0 1'b1 Off Off

Bidir: RF received

TX: Stop data. Idle only. No RF.
1'b1 1'b0 1'b0 Don’t care 1'b0 1'b0 On Off

Bidir: No link fault

TX: Transmit data and idle. No RF.

At this time, the 25G Ethernet Intel FPGA IP core does not recognize received non-zero 4-bit ordered set types as an error.

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