Visible to Intel only — GUID: lbl1457456369412
Ixiasoft
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
Visible to Intel only — GUID: lbl1457456369412
Ixiasoft
6.7. Miscellaneous Status and Debug Signals
The miscellaneous status and debug signals are asynchronous.
Signal |
Direction |
Description |
---|---|---|
tx_lanes_stable | Output | Asserted when all TX lanes are stable and ready to transmit data. |
rx_block_lock | Output | Signal is asserted when 64B/66B sync header is found consecutively for at least 64 clock cycles by the RX PCS. |
rx_am_lock | Output | If you turn on Enable RS-FEC in the parameter editor, this signal is asserted when alignment marker lock status is achieved. If you turn off Enable RS-FEC in the parameter editor, this signal behaves the same as the rx_block_lock signal. |
rx_pcs_ready | Output | Signal is asserted when rx_block_lock is asserted. |
local_fault_status | Output | Asserted when the RX MAC detects a local fault. This signal is available if you turn on Enable link fault generation in the parameter editor. |
remote_fault_status | Output | Asserted when the RX MAC detects a remote fault. This signal is available if you turn on Enable link fault generation in the parameter editor. |
unidirectional_en | Output | Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor. |
link_fault_gen_en | Output | Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor. |
Related Information