Visible to Intel only — GUID: lro1446734968432
Ixiasoft
Visible to Intel only — GUID: lro1446734968432
Ixiasoft
1.9. Minimal Preloader
The MPL initializes the PLLs, reset signals, configures IOCSR and pin MUXing, and performs other configuration-based on the preloader generator file settings. It can also load the FPGA from a boot source, if desired. It then reads a secondary image from a boot source into RAM and hands control to that image.
The MPL uses Altera HWLib drivers for most of its functionality. It also uses Altera HWLib SoCAL folders for the memory map definitions and basic read and write commands.
The example project in the following section is for Cyclone V SoC. Please modify the example as needed to select appropriate file names.