Intel® Fortran Compiler Classic and Intel® Fortran Compiler Developer Guide and Reference

ID 767251
Date 3/22/2024
Public

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Document Table of Contents

march

Tells the compiler to generate code using the CPU feature set of a specific processor as the baseline.

Syntax

Linux:

-march=processor

Windows:

None

Arguments

processor

Tells the compiler which CPU features it can use. Possible values are:

nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, gracemont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, common-avx512, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, emeraldrapids

Generates code using the CPU feature set of the specified Intel® processor or microarchitecture code name.

Keywords amberlake, coffeelake, icelake, kabylake, and whiskeylake are only available for ifort.

Note that keyword icelake is deprecated and may be removed in a future release.

x86-64

Generates code for a generic CPU with 64-bit extensions.

x86-64-v2

Generates code for Intel® SSE4.3, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3.

x86-64-v3

Generates code for Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, Intel® SSE4.3, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3.

x86-64-v4

Generates code for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), Intel® AVX-512 Doubleword and Quadword Instructions (DQI), Intel® AVX-512 Byte and Word Instructions (BWI) and Intel® AVX-512 Vector Length Extensions (VLE).

Default

OFF

If option -march is not specified, the compiler may generate Intel® SSE2 and SSE instructions.

Description

This option tells the compiler to generate code using the CPU feature set of a specific processor as the baseline.

NOTE:

This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation. Offloading can only be enabled when using ifx.

NOTE:

ifx does not support compilation for 32-bit architectures; only processor values for 64-bit instruction sets may be specified for ifx.

Product and Performance Information

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.

Notice revision #20201201

IDE Equivalent

None

Alternate Options

None

See Also