EMAC Address Map

<b> Register 0 (MAC Configuration Register)  </b>

The MAC Configuration register establishes receive and transmit operating modes.

<b> Register 1 (MAC Frame Filter) </b>

The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.

<b> Register 4 (GMII Address Register) </b> 

The GMII Address register controls the management cycles to the external PHY through the management interface.

Note: This register is present for all PHY interface when you select the Station Management (MDIO) feature in coreConsultant.

<b> Register 5 (GMII Data Register) </b>

The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4.

Note: This register is present for all PHY interface when you select the Station Management (MDIO) feature in coreConsultant.

<b> Register 6 (Flow Control Register) </b>  

The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control module. A Write to a register with the Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.

<b> Register 7 (VLAN Tag Register) </b>  

The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with 16'h8100, and the following two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive frame status. The legal length of the frame is increased from 1,518 bytes to 1,522 bytes.
If the VLAN Tag register is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to these register should be performed only after at least four clock cycles in the destination clock domain.

<b> Register 8 (Version Register) </b>  

The Version registers identifies the version of the DWC_gmac. This register contains two bytes: one that Synopsys uses to identify the core release number, and the other that you set during core configuration.

<b> Register 9 (Debug Register) </b>  

The Debug register gives the status of all main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths.

Note:  

The reset values, given for the Debug register, are valid only if the  following clocks are present during the reset operation:  
 * clk_csr_i, clk_app_i, hclk_i, or aclk_i  
 * clk_tx_i 
 * clk_rx_i

<b> Register 12 (LPI Control and Status Register) </b>  

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.

<b> Register 13 (LPI Timers Control Register) </b>  

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.

<b> Register 14 (Interrupt Register) </b>  

The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding optional feature is selected during core configuration and enabled during operation. Therefore, these bits are reserved when the corresponding features are not present in the core.

<b> Register 15 (Interrupt Mask Register) </b> 

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o in the GMAC-AHB, GMAC-AXI, and GMAC-DMA configuration and mci_intr_o in the GMAC-MTL and GMAC-CORE configuration.

<b> Register 16 (MAC Address0 High Register) </b>  

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 17 (MAC Address0 Low Register) </b>  

The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address of the station.

<b> Register 18 (MAC Address1 High Register) </b> 

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 19 (MAC Address1 Low Register) </b>  

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

<b> Register 20 (MAC Address2 High Register) </b>  

The MAC Address2 High register holds the upper 16 bits of the third 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address2 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address2 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 21 (MAC Address2 Low Register) </b>  

The MAC Address2 Low register holds the lower 32 bits of the third 6-byte MAC address of the station.

<b> Register 22 (MAC Address3 High Register) </b>  

The MAC Address3 High register holds the upper 16 bits of the fourth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address3 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address3 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 23 (MAC Address3 Low Register) </b>  

The MAC Address3 Low register holds the lower 32 bits of the fourth 6-byte MAC address of the station.

<b> Register 24 (MAC Address4 High Register) </b>  

The MAC Address4 High register holds the upper 16 bits of the fifth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address4 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address4 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 25 (MAC Address4 Low Register) </b>  

The MAC Address4 Low register holds the lower 32 bits of the fifth 6-byte MAC address of the station.

<b> Register 26 (MAC Address5 High Register) </b>

The MAC Address5 High register holds the upper 16 bits of the sixth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address5 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address5 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 27 (MAC Address5 Low Register) </b>  

The MAC Address5 Low register holds the lower 32 bits of the sixth 6-byte MAC address of the station.

<b> Register 28 (MAC Address6 High Register) </b>  

The MAC Address6 High register holds the upper 16 bits of the seventh 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address6 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address6 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 29 (MAC Address6 Low Register) </b>  

The MAC Address6 Low register holds the lower 32 bits of the seventh 6-byte MAC address of the station.

<b> Register 30 (MAC Address7 High Register) </b>  

The MAC Address7 High register holds the upper 16 bits of the eighth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address7 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address7 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 31 (MAC Address7 Low Register) </b>  

The MAC Address7 Low register holds the lower 32 bits of the eighth 6-byte MAC address of the station.

<b> Register 32 (MAC Address8 High Register) </b>  

The MAC Address8 High register holds the upper 16 bits of the nineth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address8 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address8 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 33 (MAC Address8 Low Register) </b>  

The MAC Address8 Low register holds the lower 32 bits of the nineth 6-byte MAC address of the station.

<b> Register 34 (MAC Address9 High Register) </b>  

The MAC Address9 High register holds the upper 16 bits of the tenth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address9 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address9 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 35 (MAC Address9 Low Register) </b>  

The MAC Address9 Low register holds the lower 32 bits of the tenth 6-byte MAC address of the station.

<b> Register 36 (MAC Address10 High Register) </b>  

The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address10 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address10 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 37 (MAC Address10 Low Register) </b>  

The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station.

<b> Register 38 (MAC Address11 High Register) </b>  

The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address11 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address11 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 39 (MAC Address1 Low Register) </b>  

The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station.

<b> Register 40 (MAC Address12 High Register ) </b>

The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address13 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address12 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 41 (MAC Address12 Low Register) </b>  

The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station.

<b> Register 42 (MAC Address13 High Register) </b>  

The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address13 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address13 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 43 (MAC Address13 Low Register) </b>  

The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station.

<b> Register 44 (MAC Address14 High Register) </b>  

The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address14 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 45 (MAC Address14 Low Register) </b>  

The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station.

<b> Register 46 (MAC Address15 High Register) </b> 

The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address15 Low Register should be performed after at least four clock cycles in the destination clock domain.

<b> Register 47 (MAC Address15 Low Register) </b>  

The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station.

Register 54 (SGMII/RGMII/SMII Status Register) 

<b> Register 64 (MMC Control Register) </b>

The MMC Control register establishes the operating mode of the management counters.

Note:
The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.

<b> Register 65 (MMC Receive Interrupt Register) </b>

The MMC Receive Interrupt register maintains the interrupts that are generated when the following happens:
 * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter).
 * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). 
When the Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.

<b> Register 66 (MMC Transmit Interrupt Register) </b>

The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.

Regsiter 67 (MMC Receive Interrupt Mask Register)

The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.

<b> Register 68 (MMC Transmit Interrupt Mask Register) </b>

The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.

<b> Register 69 (Transmit Octet Count for Good and Bad Frames) </b>

This register maintains the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes.

<b> Register 70 (Transmit Frame Count for Good and Bad Frames) </b>

This register maintains the number of good and bad frames transmitted, exclusive of retried frames.

<b> Register 71 (Transmit Frame Count for Good Broadcast Frames) </b>

This register maintains the number of transmitted good broadcast frames.

<b> Register 72 (Transmit Frame Count for Good Multicast Frames) </b>

This register maintains the number of transmitted good multicast frames.

<b> Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames) </b>

This register maintains the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames.

<b> Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames) </b>

This register maintains the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames.

<b> Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames) </b>

This register maintains the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames.

<b> Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames) </b>

This register maintains the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames.

<b> Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames) </b>

This register maintains the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames.

<b> Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames) </b>

This register maintains the number of transmitted good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames.

<b> Register 79 (Transmit Frame Count for Good and Bad Unicast Frames) </b>

This register maintains the number of transmitted good and bad unicast frames.

<b> Register 80 (Transmit Frame Count for Good and Bad Multicast Frames) </b>

This register maintains the number of transmitted good and bad multicast frames.

<b> Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames) </b>

This register maintains the number of transmitted good and bad broadcast frames.

<b> Register 82 (Transmit Frame Count for Underflow Error Frames) </b>

This register maintains the number of frames aborted because of frame underflow error.

<b> Register 83 (Transmit Frame Count for Frames Transmitted after Single Collision) </b>

This register maintains the number of successfully transmitted frames after a single collision in the half-duplex mode.

<b> Register 84 (Transmit Frame Count for Frames Transmitted after Multiple Collision) </b>

This register maintains the number of successfully transmitted frames after multiple collisions in the half-duplex mode.

<b> Register 85 (Transmit Frame Count for Deferred Frames) </b>

This register maintains the number of successfully transmitted frames after a deferral in the half-duplex mode.

<b> Register 86 (Transmit Frame Count for Late Collision Error Frames) </b>

This register maintains the number of frames aborted because of late collision error.

<b> Register 87 (Transmit Frame Count for Excessive Collision Error Frames) </b>

This register maintains the number of frames aborted because of excessive (16) collision error.

<b> Register 88 (Transmit Frame Count for Carrier Sense Error Frames) </b>

This register maintains the number of frames aborted because of carrier sense error (no carrier or loss of carrier).

<b> Register 89 (Transmit Octet Count for Good Frames) </b>

This register maintains the number of bytes transmitted, exclusive of preamble, in good frames.

<b> Register 90 (Transmit Frame Count for Good Frames) </b>

This register maintains the number of transmitted good frames, exclusive of preamble.

<b> Register 91 (Transmit Frame Count for Excessive Deferral Error Frames) </b>

This register maintains the number of frames aborted because of  excessive deferral error, that is, frames deferred for more than two max-sized frame times.

<b> Register 92 (Transmit Frame Count for Good PAUSE Frames) </b>

This register maintains the number of transmitted good PAUSE frames.

<b> Register 93 (Transmit Frame Count for Good VLAN Frames) </b>

This register maintains the number of transmitted good VLAN frames, exclusive of retried frames.

<b> Register 94 (Transmit Frame Count for Good Oversize Frames) </b>

This register maintains the number of transmitted good Oversize frames, exclusive of retried frames.

<b> Register 96 (Receive Frame Count for Good and Bad Frames) </b>

This register maintains the number of received good and bad frames.

<b> Register 97 (Receive Octet Count for Good and Bad Frames) </b>

This register maintains the number of bytes received, exclusive of preamble, in good and bad frames.

<b> Register 98 (Receive Octet Count for Good Frames) </b> 

This register maintains the number of bytes received, exclusive of preamble, only in good frames.

<b> Register 99 (Receive Frame Count for Good Broadcast Frames) </b> 

This register maintains the number of received good broadcast frames.

<b> Register 100 (Receive Frame Count for Good Multicast Frames) </b> 

This register maintains the number of received good multicast frames.

<b> Register 101 (Receive Frame Count for CRC Error Frames) </b>

This register maintains the number of frames received with CRC error.

<b> Register 102 (Receive Frame Count for Alignment Error Frames) </b>

This register maintains the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode.

<b> Register 103 (Receive Frame Count for Runt Error Frames) </b>

This register maintains the number of frames received with runt error(<64 bytes and CRC error).

<b> Register 104 (Receive Frame Count for Jabber Error Frames) </b>

This register maintains the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames.

<b> Register 105 (Receive Frame Count for Undersize Frames) </b>

This register maintains the number of frames received with length less than 64 bytes and without errors.

<b> Register 106 (Receive Frame Count for Oversize Frames) </b>

This register maintains the number of frames received with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames) and without errors.

<b> Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames) </b>

This register maintains the number of received good and bad frames with length 64 bytes, exclusive of preamble.

<b> Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames) </b>

This register maintains the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble.

<b> Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames) </b>

This register maintains the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble.

<b> Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames) </b>

This register maintains the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble.

<b> Register 111 (Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames) </b>

This register maintains the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble.

<b> Register 112 (Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames) </b>

This register maintains the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble.

<b> Register 113 (Receive Frame Count for Good Unicast Frames)  </b>

This register maintains the number of received good unicast frames.

<b> Register 114 (Receive Frame Count for Length Error Frames)  </b>

This register maintains the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field.

<b> Register 115 (Receive Frame Count for Out of Range Frames)  </b>

This register maintains the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536).

<b> Register 116 (Receive Frame Count for PAUSE Frames)  </b>

This register maintains the number of received good and valid PAUSE frames.

<b> Register 117 (Receive Frame Count for FIFO Overflow Frames) </b>

This register maintains the number of received frames missed because of FIFO overflow.

<b> Register 118 (Receive Frame Count for Good and Bad VLAN Frames) </b>

This register maintains the number of received good and bad VLAN frames.

<b> Register 119 (Receive Frame Count for Watchdog Error Frames) </b>

This register maintains the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes or value programmed in Register 55 (Watchdog Timeout Register)).

<b> Register 120 (Receive Frame Count for Receive Error Frames) </b>
This register maintains the number of frames received with error because of the GMII/MII RXER error.

<b> Register 121 (Receive Frame Count for Good Control Frames Frames) </b>

This register maintains the number of good control frames received.

Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) 

Register 130 (MMC Receive Checksum Offload Interrupt Register) 

Register 132 (rxipv4_gd_frms Register)

Register 133 (rxipv4_hdrerr_frms Register)

Register 134 (rxipv4_nopay_frms Register)

Register 135 (rxipv4_frag_frms Register)

Register 136 (rxipv4_udsbl_frms Register)

Register 137 (rxipv6_gd_frms Register)

Register 138 (rxipv6_hdrerr_frms Register)

Register 139 (rxipv6_nopay_frms)

Register 140 (rxudp_gd_frms Register)

Register 141 (rxudp_err_frms Register)

Register 142 (rxtcp_gd_frms Register)

Register 143 (rxtcp_err_frms Register)

Register 144 (rxicmp_gd_frms Register)

Register 145 (rxicmp_err_frms Register)

Register 148 (rxipv4_gd_octets Register)

Register 149 (rxipv4_hdrerr_octets)

Register 150 (rxipv4_nopay_octets Register)

Register 151 (rxipv4_frag_octets Register)

Register 152 (rxipv4_udsbl_octets Register)

Register 153 (rxipv6_gd_octets Register)

Register 154 (rxipv6_hdrerr_octets Register)

Register 155 (rxipv6_nopay_octets Register)

Register 156 (rxudp_gd_octets Register)

Register 157 (rxudp_err_octets Register)

Register 158 (rxtcp_gd_octets Register)

Register 159 (rxtcp_err_octets Register)

Register 160 (rxicmp_gd_octets Register)

Register 161 (rxicmp_err_octets Register)

<b> Register 256 (Layer 3 and Layer 4 Control Register 0) </b>

This register controls the operations of the filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.

<b> Register 257 (Layer 4 Address Register 0) 
</b>

You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option in coreConsultant. If the Layer 3 and Layer 4 Address Registers are configured to be double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this register and registers 260 through 299 are reserved (RO with default value).

<b> Register 260 (Layer 3 Address 0 Register 0) </b>

For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

<b> Register 261 (Layer 3 Address 1 Register 0) </b>

For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

<b> Register 262 (Layer 3 Address 2 Register 0) </b>

For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.

<b> Register 263 (Layer 3 Address 3 Register 0) </b>

For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.

Register 268 (Layer 3 and Layer 4 Control Register 1) 

Register 269 (Layer 4 Address Register 1)  

Register 272 (Layer 3 Address 0 Register 1) 

Register 273 (Layer 3 Address 1 Register 1) 

Register 274 (Layer 3 Address 2 Register 1) 

Register 275 (Layer 3 Address 3 Register 1) 

Register 280 (Layer 3 and Layer 4 Control Register 2) 

Register 281 (Layer 4 Address Register 2) 

Register 284 (Layer 3 Address 0 Register 2) 

Register 285 (Layer 3 Address 1 Register 2) 

Register 286 (Layer 3 Address 2 Register 2) 

Register 287 (Layer 3 Address 3 Register 2) 

Register 292 (Layer 3 and Layer 4 Control Register 3) 

Register 293 (Layer 4 Address Register 3)  

Register 296 (Layer 3 Address 0 Register 3) 

Register 297 (Layer 3 Address 1 Register 3) 

Register 298 (Layer 3 Address 2 Register 3) 

Register 299 (Layer 3 Address 3 Register 3) 

Register 320 (Hash Table Register 0) 

Register 321 (Hash Table Register 1) 

Register 322 (Hash Table Register 2) 

Register 323 (Hash Table Register 3) 

Register 324 (Hash Table Register 4) 

Register 325 (Hash Table Register 5) 

Register 326 (Hash Table Register 6) 

Register 327 (Hash Table Register 7) 

<b> Register 353 (VLAN Tag Inclusion or Replacement Register)  </b>

The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the transmit frames. This register is present only when the Enable SA, VLAN, and CRC Insertion on TX option is selected during core configuration.

Register 354 (VLAN Hash Table Register) 

<b> Register 448 (Timestamp Control Register) </b>

This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.

Note: 
 * Bits[5:1] are reserved when External Timestamp Input feature is enabled. 
 * Bits[19:8] are reserved and read-only when Advanced Timestamp feature is not enabled.
 * Bits[28:24] are reserved and read-only when Auxiliary Snapshot feature is not enabled.
 * Release 3.60a onwards, the functions of Bits 17 and 16 (SNAPTYPSEL) have changed. These functions are not backward compatible with the functions described in release 3.50a.

Register 449 (Sub-Second Increment Register) 

Register 450 (System Time - Seconds Register) 

Register 451 (System Time - Nanoseconds Register) 

Register 452 (System Time - Seconds Update Register)  

Register 453 (System Time - Nanoseconds Update Register) 

Register 454 (Timestamp Addend Register) 

Register 455 (Target Time Seconds Register) 

Register 456 (Target Time Nanoseconds Register) 

Register 457 (System Time - Higher Word Seconds Register) 

Register 458 (Timestamp Status Register)  

Register 459 (PPS Control Register) 

Register 460 (Auxiliary Timestamp - Nanoseconds Register) 

Register 461 (Auxiliary Timestamp - Seconds Register)  

Register 472 (PPS0 Interval Register) 

Register 473 (PPS0 Width Register) 

<b> Register 512 (MAC Address16 High Register) </b>  

The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address16 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address16 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 513 (MAC Address16 Low Register) </b>  

The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station.

<b> Register 514 (MAC Address17 High Register) </b>  

The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address17 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address17 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 515 (MAC Address17 Low Register) </b>  

The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station.

<b> Register 516 (MAC Address18 High Register) </b>  

The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address18 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address18 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 517 (MAC Address18 Low Register) </b>  

The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station.

<b> Register 518 (MAC Address19 High Register) </b>  

The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address19 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address19 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 519 (MAC Address19 Low Register) </b>  

The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station.

<b> Register 520 (MAC Address20 High Register) </b>  

The MAC Address20 High register holds the upper 16 bits of the 21st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address20 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address20 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 521 (MAC Address20 Low Register) </b>  

The MAC Address20 Low register holds the lower 32 bits of the 21st 6-byte MAC address of the station.

<b> Register 522 (MAC Address21 High Register) </b>  

The MAC Address21 High register holds the upper 16 bits of the 22nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address21 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address21 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 523 (MAC Address21 Low Register) </b>  

The MAC Address21 Low register holds the lower 32 bits of the 22nd 6-byte MAC address of the station.

<b> Register 524 (MAC Address22 High Register) </b>  

The MAC Address22 High register holds the upper 16 bits of the 23rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address22 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address22 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 525 (MAC Address22 Low Register) </b>  

The MAC Address22 Low register holds the lower 32 bits of the 23rd 6-byte MAC address of the station.

<b> Register 526 (MAC Address23 High Register   </b>

The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address23 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address23 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 527 (MAC Address23 Low Register) </b> 

The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station.

<b> Register 528 (MAC Address24 High Register) </b>  

The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address24 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address24 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 529 (MAC Address24 Low Register) </b>  

The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station.

<b> Register 530 (MAC Address25 High Register) </b>  

The MAC Address25 High register holds the upper 16 bits of the 6-byte 26th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address25 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address25 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 531 (MAC Address25 Low Register) </b>  

The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station.

<b> Register 532 (MAC Address26 High Register) </b>  

The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address26 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address26 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 533 (MAC Address26 Low Register) </b>

The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station.

<b> Register 534 (MAC Address27 High Register) </b>  

The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address27 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address27 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 535 (MAC Address27 Low Register) </b>  

The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station.

<b> Register 536 (MAC Address28 High Register) </b>  

The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address28 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address28 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 537 (MAC Address28 Low Register) </b>  

The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station.

<b> Register 538 (MAC Address29 High Register) </b>  

The MAC Address29 High register holds the upper 16 bits of the 6-byte 30th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address29 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address29 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 539 (MAC Address29 Low Register) </b>  

The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station.

<b> Register 540 (MAC Address30 High Register) </b>  

The MAC Address30 High register holds the upper 16 bits of the 31st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address30 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address30 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 541 (MAC Address30 Low Register) </b>  

The MAC Address30 Low register holds the lower 32 bits of the 31st 6-byte MAC address of the station.

<b> Register 542 (MAC Address31 High Register) </b>

The MAC Address31 High register holds the upper 16 bits of the 32nd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address31 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address31 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 543 (MAC Address31 Low Register) </b>  

The MAC Address31 Low register holds the lower 32 bits of the 32nd 6-byte MAC address of the station.

<b> Register 544 (MAC Address32 High Register) </b>  

The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address32 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address32 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 545 (MAC Address32 Low Register) </b>  

The MAC Address32 Low register holds the lower 32 bits of the 33rd 6-byte MAC address of the station.

<b> Register 546 (MAC Address33 High Register) </b>  

The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address33 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address33 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 547 (MAC Address33 Low Register) </b>

The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC address of the station.

<b> Register 548 (MAC Address34 High Register) </b>  

The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address34 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address34 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 549 (MAC Address34 Low Register) </b>  

The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC address of the station.

<b> Register 550 (MAC Address35 High Register) </b>  

The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address35 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address35 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 551 (MAC Address35 Low Register) </b>  

The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC address of the station.

<b> Register 552 (MAC Address36 High Register) </b>  

The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address36 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address36 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 553 (MAC Address36 Low Register) </b>  

The MAC Address36 Low register holds the lower 32 bits of the 34th 6-byte MAC address of the station.

<b> Register 554 (MAC Address37 High Register) </b>  

The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address37 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address37 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 555 (MAC Address37 Low Register) </b>

The MAC Address37 Low register holds the lower 32 bits of the 37th 6-byte MAC address of the station.

<b> Register 556 (MAC Address38 High Register) </b>  

The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address38 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address38 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 557 (MAC Address38 Low Register) </b>  

The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC address of the station.

<b> Register 558 (MAC Address39 High Register) </b>

The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address40 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address40 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 559 (MAC Address39 Low Register) </b>  

The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC address of the station.

<b> Register 560 (MAC Address40 High Register) </b>  

The MAC Address40 High register holds the upper 16 bits of the 41st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address40 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address40 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 561 (MAC Address40 Low Register) </b> 

The MAC Address40 Low register holds the lower 32 bits of the 41st 6-byte MAC address of the station.

<b> Register 562 (MAC Address41 High Register) </b>  

The MAC Address41 High register holds the upper 16 bits of the 42nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address41 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address41 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 563 (MAC Address41 Low Register) </b>  

The MAC Address41 Low register holds the lower 32 bits of the 42nd 6-byte MAC address of the station.

<b> Register 564 (MAC Address42 High Register) </b>  

The MAC Address42 High register holds the upper 16 bits of the 43rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address42 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address42 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 565 (MAC Address42 Low Register) </b> 

The MAC Address42 Low register holds the lower 32 bits of the 43rd 6-byte MAC address of the station.

<b> Register 566 (MAC Address43 High Register) </b>  

The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address43 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address43 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 567 (MAC Address43 Low Register) </b>

The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC address of the station.

<b> Register 568 (MAC Address44 High Register) </b>  

The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address44 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address44 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 569 (MAC Address44 Low Register) </b> 

The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC address of the station.

<b> Register 570 (MAC Address45 High Register) </b>  

The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address45 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address45 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 571 (MAC Address45 Low Register) </b>  

The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC address of the station.

<b> Register 572 (MAC Address46 High Register) </b>  

The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address46 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address46 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 573 (MAC Address46 Low Register) </b>  

The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC address of the station.

<b> Register 574 (MAC Address47 High Register) </b>  

The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address47 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address47 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 575 (MAC Address47 Low Register) </b>  

The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC address of the station.

<b> Register 576 (MAC Address48 High Register) </b>  

The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address48 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address48 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 577 (MAC Address48 Low Register) </b>  

The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC address of the station.

<b> Register 578 (MAC Address49 High Register) </b>  

The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address49 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address49 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 579 (MAC Address49 Low Register) </b>  

The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC address of the station.

<b> Register 580 (MAC Address50 High Register) </b>  

The MAC Address50 High register holds the upper 16 bits of the 51st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address50 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address50 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 581 (MAC Address50 Low Register) </b>  

The MAC Address50 Low register holds the lower 32 bits of the 51st 6-byte MAC address of the station.

<b> Register 582 (MAC Address51 High Register) </b>  

The MAC Address51 High register holds the upper 16 bits of the 52nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address51 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address51 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 583 (MAC Address51 Low Register) </b>  

The MAC Address51 Low register holds the lower 32 bits of the 52nd 6-byte MAC address of the station.

<b> Register 584 (MAC Address52 High Register) </b>  

The MAC Address52 High register holds the upper 16 bits of the 53rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address52 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address52 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 585 (MAC Address52 Low Register) </b>

The MAC Address52 Low register holds the lower 32 bits of the 53rd 6-byte MAC address of the station.

<b> Register 586 (MAC Address53 High Register)</b> 

The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address53 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address53 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 587 (MAC Address53 Low Register)</b>  

The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC address of the station.

<b> Register 588 (MAC Address54 High Register)</b>  

The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address54 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address54 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 589 (MAC Address54 Low Register)</b>  

The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC address of the station.

<b> Register 590 (MAC Address55 High Register) </b>  

The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address55 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address55 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 591 (MAC Address55 Low Register) </b>  

The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC address of the station.

<b> Register 592 (MAC Address56 High Register) </b>  

The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address56 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address56 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 593 (MAC Address56 Low Register) </b>  

The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC address of the station.

<b> Register 594 (MAC Address57 High Register) </b>  

The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address57 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address57 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 595 (MAC Address57 Low Register)</b>  

The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC address of the station.

<b> Register 596 (MAC Address58 High Register)</b>  

The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address58 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address58 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 597 (MAC Address58 Low Register)</b>  

The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC address of the station.

<b> Register 598 (MAC Address59 High Register) </b>  

The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address59 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address59 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 599 (MAC Address59 Low Register) </b>  

The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC address of the station.

<b> Register 600 (MAC Address60 High Register) </b>  

The MAC Address60 High register holds the upper 16 bits of the 61st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address60 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address60 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 601 (MAC Address60 Low Register) </b>  

The MAC Address60 Low register holds the lower 32 bits of the 61st 6-byte MAC address of the station.

<b> Register 602 (MAC Address61 High Register) </b>  

The MAC Address61 High register holds the upper 16 bits of the 62nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address61 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address61 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 603 (MAC Address61 Low Register)</b>  

The MAC Address61 Low register holds the lower 32 bits of the 62nd 6-byte MAC address of the station.

<b> Register 604 (MAC Address62 High Register)</b>  

The MAC Address62 High register holds the upper 16 bits of the 63rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address62 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address62 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 605 (MAC Address62 Low Register)</b>  

The MAC Address62 Low register holds the lower 32 bits of the 63rd 6-byte MAC address of the station.

<b> Register 606 (MAC Address63 High Register) </b>  

The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address63 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address63 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 607 (MAC Address63 Low Register) </b>  

The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC address of the station.

<b> Register 608 (MAC Address64 High Register) </b>  

The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address64 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address64 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 609 (MAC Address64 Low Register) </b> 

The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC address of the station.

<b> Register 610 (MAC Address65 High Register) </b>  

The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address65 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address65 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 611 (MAC Address65 Low Register)</b>  

The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC address of the station.

<b> Register 612 (MAC Address66 High Register)</b>  

The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address66 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address66 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 613 (MAC Address66 Low Register)</b>  

The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC address of the station.

<b> Register 614 (MAC Address67 High Register)</b>  

The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address67 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address67 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 615 (MAC Address67 Low Register)</b>  

The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC address of the station.

<b> Register 616 (MAC Address68 High Register)</b>  

The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address68 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address68 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 617 (MAC Address68 Low Register)</b>  

The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC address of the station.

<b> Register 618 (MAC Address69 High Register) </b>  

The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address69 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address70 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 619 (MAC Address69 Low Register) </b>  

The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC address of the station.

<b> Register 620 (MAC Address70 High Register) </b>  

The MAC Address70 High register holds the upper 16 bits of the 71st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address70 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address70 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 621 (MAC Address70 Low Register) </b>  

The MAC Address70 Low register holds the lower 32 bits of the 71st 6-byte MAC address of the station.

<b> Register 622 (MAC Address71 High Register) </b>  

The MAC Address71 High register holds the upper 16 bits of the 72nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address71 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address71 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 623 (MAC Address71 Low Register)</b>  

The MAC Address71 Low register holds the lower 32 bits of the 72nd 6-byte MAC address of the station.

<b> Register 624 (MAC Address72 High Register)</b>  

The MAC Address72 High register holds the upper 16 bits of the 73rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address72 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address72 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 625 (MAC Address72 Low Register)</b>  

The MAC Address72 Low register holds the lower 32 bits of the 73rd 6-byte MAC address of the station.

<b> Register 626 (MAC Address73 High Register)</b>  

The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address73 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address73 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 627 (MAC Address73 Low Register)</b>  

The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC address of the station.

<b> Register 628 (MAC Address74 High Register)</b>  

The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address74 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address74 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 629 (MAC Address74 Low Register)</b> 

The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC address of the station.

<b> Register 630 (MAC Address75 High Register) </b>  

The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address75 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address75 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 631 (MAC Address75 Low Register) </b>  

The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC address of the station.

<b> Register 632 (MAC Address76 High Register) </b>  

The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address76 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address76 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 633 (MAC Address76 Low Register) </b>  

The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC address of the station.

<b> Register 634 (MAC Address77 High Register) </b>  

The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address77 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address77 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 635 (MAC Address77 Low Register)</b>  

The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC address of the station.

<b> Register 636 (MAC Address78 High Register)</b>  

The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address78 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address78 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 637 (MAC Address78 Low Register)</b>  

The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC address of the station.

<b> Register 638 (MAC Address79 High Register)</b>  

The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address79 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address79 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 639 (MAC Address79 Low Register)</b>  

The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC address of the station.

<b> Register 640 (MAC Address80 High Register)</b>  

The MAC Address80 High register holds the upper 16 bits of the 81st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address80 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address80 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 641 (MAC Address80 Low Register) </b> 
  

The MAC Address80 Low register holds the lower 32 bits of the 81st 6-byte MAC address of the station.

<b> Register 642 (MAC Address81 High Register) </b>  

The MAC Address81 High register holds the upper 16 bits of the 82nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address81 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address81 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 643 (MAC Address81 Low Register) </b>  

The MAC Address81 Low register holds the lower 32 bits of the 82nd 6-byte MAC address of the station.

<b> Register 644 (MAC Address82 High Register) </b>  

The MAC Address82 High register holds the upper 16 bits of the 83rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address82 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address82 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 645 (MAC Address82 Low Register) </b>  

The MAC Address82 Low register holds the lower 32 bits of the 83rd 6-byte MAC address of the station.

<b> Register 646 (MAC Address83 High Register) </b>  

The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address83 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address83 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 647 (MAC Address83 Low Register)</b>  

The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC address of the station.

<b> Register 648 (MAC Address84 High Register)</b>  

The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address84 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address84 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 649 (MAC Address84 Low Register)</b>  

The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC address of the station.

<b> Register 650 (MAC Address85 High Register)</b>  

The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address85 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address85 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 651 (MAC Address85 Low Register)</b>  

The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC address of the station.

<b> Register 652 (MAC Address86 High Register)</b>  

The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address86 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address86 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 653 (MAC Address86 Low Register)</b>
  

The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC address of the station.

<b> Register 654 (MAC Address87 High Register)</b>
  

The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address87 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address87 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 655 (MAC Address87 Low Register)</b>
  

The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC address of the station.

<b> Register 656 (MAC Address88 High Register)</b>
  

The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address88 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address88 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 657 (MAC Address88 Low Register)</b>
  

The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC address of the station.

<b> Register 658 (MAC Address89 High Register)</b>
  

The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address89 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address89 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 659 (MAC Address89 Low Register)</b>
  

The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC address of the station.

<b> Register 660 (MAC Address90 High Register)</b>
  

The MAC Address90 High register holds the upper 16 bits of the 91st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address90 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address90 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 661 (MAC Address90 Low Register)</b>
  

The MAC Address90 Low register holds the lower 32 bits of the 91st 6-byte MAC address of the station.

<b> Register 662 (MAC Address91 High Register)</b>
  

The MAC Address91 High register holds the upper 16 bits of the 92nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address32 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address91 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 663 (MAC Address91 Low Register)</b>
  

The MAC Address91 Low register holds the lower 32 bits of the 92nd 6-byte MAC address of the station.

<b> Register 664 (MAC Address92 High Register)</b>
  

The MAC Address92 High register holds the upper 16 bits of the 93rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address92 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address92 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 665 (MAC Address92 Low Register)</b>
  

The MAC Address92 Low register holds the lower 32 bits of the 93rd 6-byte MAC address of the station.

<b> Register 666 (MAC Address93 High Register)</b>
  

The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address93 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address93 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 667 (MAC Address93 Low Register)</b>
  

The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC address of the station.

<b> Register 668 (MAC Address94 High Register)</b>
  

The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address94 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address94 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 669 (MAC Address94 Low Register)</b>
  

The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC address of the station.

<b> Register 670 (MAC Address95 High Register)</b>
  

The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address95 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address95 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 671 (MAC Address95 Low Register)</b>
  

The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC address of the station.

<b> Register 672 (MAC Address96 High Register)</b>
  

The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address96 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address96 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 673 (MAC Address96 Low Register)</b>
  

The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC address of the station.

<b> Register 674 (MAC Address97 High Register)</b>
  

The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address97 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address97 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 675 (MAC Address97 Low Register)</b>
  

The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC address of the station.

<b> Register 676 (MAC Address98 High Register)</b>
  

The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address99 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address99 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 677 (MAC Address98 Low Register)</b>
  

The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC address of the station.

<b> Register 678 (MAC Address99 High Register)</b>

The MAC Address99 High register holds the upper 16 bits of the 6-byte 100th MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address99 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address99 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 679 (MAC Address99 Low Register)</b>
  

The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC address of the station.

<b> Register 680 (MAC Address100 High Register)</b>
  

The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address100 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address100 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 681 (MAC Address100 Low Register)</b>
  

The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC address of the station.

<b> Register 682 (MAC Address101 High Register)</b>
  

The MAC Address101 High register holds the upper 16 bits of the 102nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address101 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address101 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 683 (MAC Address101 Low Register)</b>
  

The MAC Address101 Low register holds the lower 32 bits of the 102nd 6-byte MAC address of the station.

<b> Register 684 (MAC Address102 High Register)</b>
  

The MAC Address102 High register holds the upper 16 bits of the 6-byte 103rd MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address102 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address102 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 685 (MAC Address102 Low Register)</b>
  

The MAC Address102 Low register holds the lower 32 bits of the 103rd 6-byte MAC address of the station.

<b> Register 686 (MAC Address103 High Register)</b>
  

The MAC Address103 High register holds the upper 16 bits of the 6-byte 104th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address103 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address103 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 687 (MAC Address103 Low Register)</b>
  

The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC address of the station.

<b> Register 688 (MAC Address104 High Register)</b>
  

The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address104 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address104 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 689 (MAC Address104 Low Register)</b>
  

The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC address of the station.

<b> Register 690 (MAC Address105 High Register)</b>
  

The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address105 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address105 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 691 (MAC Address105 Low Register)</b>
  

The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC address of the station.

<b> Register 692 (MAC Address106 High Register)</b>
  

The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address106 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address106 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 693 (MAC Address106 Low Register)</b>
  

The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC address of the station.

<b> Register 694 (MAC Address107 High Register)</b>
  

The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address107 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address107 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 695 (MAC Address107 Low Register)</b>
  

The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC address of the station.

<b> Register 696 (MAC Address108 High Register)</b>
  

The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address108 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address108 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 697 (MAC Address108 Low Register)</b>
  

The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC address of the station.

<b> Register 698 (MAC Address109 High Register)</b>
  

The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address109 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address109 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 699 (MAC Address109 Low Register)</b>
  

The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC address of the station.

<b> Register XXX (MAC AddressXX High Register)</b>
  

The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address110 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address110 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 700 (MAC Address110 Low Register)</b>
  

The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC address of the station.

<b> Register 701 (MAC Address111 High Register)</b>
  

The MAC Address111 High register holds the upper 16 bits of the 6-byte 112th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address111 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address111 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 702 (MAC Address111 Low Register)</b>
  

The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC address of the station.

<b> Register 703 (MAC Address112 High Register)</b>
  

The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address112 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address112 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 704 (MAC Address112 Low Register)</b>
  

The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC address of the station.

<b> Register 705 (MAC Address113 High Register)</b>
  

The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address113 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address113 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 706 (MAC Address113 Low Register)</b>
  

The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC address of the station.

<b> Register 707 (MAC Address114 High Register)</b>
  

The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address114 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address114 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 708 (MAC Address114 Low Register)</b>
  

The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC address of the station.

<b> Register 709 (MAC Address115 High Register)</b>
  

The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address115 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address115 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 710 (MAC Address115 Low Register)</b>
  

The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC address of the station.

<b> Register 711 (MAC Address116 High Register)</b>
  

The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address116 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address116 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 712 (MAC Address116 Low Register)</b>
  

The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC address of the station.

<b> Register 713 (MAC Address117 High Register)</b>
  

The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address117 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address117 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 714 (MAC Address117 Low Register)</b>
  

The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC address of the station.

<b> Register 715 (MAC Address118 High Register)</b>
  

The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address118 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address118 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 716 (MAC Address118 Low Register)</b>
  

The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC address of the station.

<b> Register 717 (MAC Address119 High Register)</b>
  

The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address119 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address119 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 718 (MAC Address119 Low Register)</b>
  

The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC address of the station.

<b> Register 719 (MAC Address120 High Register)</b>
  

The MAC Address120 High register holds the upper 16 bits of the 6-byte 121st MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address120 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address120 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 720 (MAC Address120 Low Register)</b>
  

The MAC Address120 Low register holds the lower 32 bits of the 121st 6-byte MAC address of the station.

<b> Register 721 (MAC Address121 High Register)</b>
  

The MAC Address121 High register holds the upper 16 bits of the 122nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address121 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address121 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 722 (MAC Address121 Low Register)</b>
  

The MAC Address121 Low register holds the lower 32 bits of the 122nd 6-byte MAC address of the station.

<b> Register 723 (MAC Address122 High Register)</b>
  

The MAC Address122 High register holds the upper 16 bits of the 123rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address122 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address122 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 724 (MAC Address122 Low Register)</b>
  

The MAC Address122 Low register holds the lower 32 bits of the 123rd 6-byte MAC address of the station.

<b> Register 725 (MAC Address123 High Register)</b>
  

The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address123 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address123 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 726 (MAC AddressXX 123 Register)</b>
  

The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC address of the station.

<b> Register 727 (MAC Address124 High Register)</b>
  

The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address124 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address124 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 728 (MAC Address124 Low Register)</b>
  

The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC address of the station.

<b> Register 729 (MAC Address125 High Register)</b>
  

The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address125 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address125 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 730 (MAC Address125 Low Register)</b>
  

The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC address of the station.

<b> Register 731 (MAC Address126 High Register)</b>
  

The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address126 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address126 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 732 (MAC Address126 Low Register)</b>
  

The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC address of the station.

<b> Register 733 (MAC Address127 High Register)</b>
  

The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address127 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address127 Low Register must be performed after at least four clock cycles in the destination clock domain.

<b> Register 734 (MAC Address127 Low Register)</b>
  

The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC address of the station.

<b> Register 0 (Bus Mode Register) </b>

The Bus Mode register establishes the bus operating modes for the DMA.

<b> Register 1 (Transmit Poll Demand Register) </b>

The Transmit Poll Demand register enables the Tx DMA to check whether or not the DMA owns the current descriptor. The Transmit Poll Demand command is given to wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the Suspend mode because of an Underflow error in a transmitted frame or the unavailability of descriptors owned by it. You can give this command anytime and the Tx DMA resets this command when it again starts fetching the current descriptor from host memory. When this register is read, it always returns zero.

<b>Register 2 (Receive Poll Demand Register) </b>

The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is used to wake up the Rx DMA from the SUSPEND state. The RxDMA can go into the SUSPEND state only because of the unavailability of descriptors it owns. When this register is read, it always returns zero.

<b>Register 3 (Receive Descriptor List Address Register) </b>

The Receive Descriptor List Address register points to the start of the Receive Descriptor List. The descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given.

You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can be written with a new descriptor list address. When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.

If this register is not changed when the SR bit is set to 0, then the DMA takes the descriptor address where it was stopped earlier.

<b>Register 4 (Transmit Descriptor List Address Register)</b>

The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low. 

You can write to this register only when the Tx DMA has stopped, that is, Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly programmed descriptor base address.

If this register is not changed when the ST bit is set to 0, then the DMA takes the descriptor address where it was stopped earlier.

<b>Register 5 (Status Register) </b> 

The Status register contains all status bits that the DMA reports to the host. The Software driver reads this register during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The bits of this register are not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit in Register 7 (Interrupt Enable Register).

<b> Register 6 (Operation Mode Register) </b>

The Operation Mode register establishes the Transmit and Receive operating modes and commands. This register should be the last CSR to be written as part of the DMA initialization. This register is also present in the GMAC-MTL configuration with unused and reserved bits 24, 13, 2, and 1.

<b> Register 7 (Interrupt Enable Register) </b>

The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.

<b>Register 8 (Missed Frame and Buffer Overflow Counter Register) </b>

The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.

<b> Register 9 (Receive Interrupt Watchdog Timer Register) </b>

This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt (Bit 6) of Register 5 (Status Register)

Register 10 (AXI Bus Mode Register) 

<b> Register 11 (AHB or AXI Status Register) </b>

This register provides the active status of the AHB master interface or AXI interface's read and write channels. This register is present and valid only in the GMAC-AHB and GMAC-AXI configurations. This register is useful for debugging purposes. In addition, this register is valid only in the Channel 0 DMA when multiple channels are present in the AV mode.

<b> Register 18 (Current Host Transmit Descriptor Register) </b>

The Current Host Transmit Descriptor register points to the start address of the current Transmit Descriptor read by the DMA.

<b> Register 19 (Current Host Receive Descriptor Register) </b>

The Current Host Receive Descriptor register points to the start address of the current Receive Descriptor read by the DMA.

<b> Register 20 (Current Host Transmit Buffer Address Register) </b>

The Current Host Transmit Buffer Address register points to the current Transmit Buffer Address being read by the DMA.

<b> Register 21 (Current Host Receive Buffer Address Register) </b>

The Current Host Receive Buffer Address register points to the current Receive Buffer address being read by the DMA.

<b> Register 22 (HW Feature Register) </b>

This register indicates the presence of the optional features or functions of the DWC_gmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Note: All bits are set or reset as per the selection of features during the DWC_gmac configuration.

<b> Register 55 (Watchdog Timeout Register) </b>
This register controls the watchdog timeout for received frames.

<b> Register 56 (General Purpose IO Register) </b>
This register provides the control to drive up to 4 bits of output ports (GPO) and the status of up to 4 input
ports (GPIS). It also provides the control to generate interrupts on events occurring on the gpi_i pin.