gmacgrp_lpi_control_status 

         <b> Register 12 (LPI Control and Status Register) </b>  

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800030
i_emac_emac1 0xFF802000 0xFF802030
i_emac_emac2 0xFF804000 0xFF804030

Size: 32

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_20

RO 0x0

lpitxa

RW 0x0

plsen

RO 0x0

pls

RW 0x0

lpien

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_10

RO 0x0

rlpist

RO 0x0

tlpist

RO 0x0

reserved_7_4

RO 0x0

rlpiex

RO 0x0

rlpien

RO 0x0

tlpiex

RO 0x0

tlpien

RO 0x0

gmacgrp_lpi_control_status Fields

Bit Name Description Access Reset
31:20 reserved_31_20 
Reserved
 RO 0x0
19 lpitxa 
LPI TX Automate

This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. 
If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode.

When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
18 plsen 
PHY Link Status Enable

This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. 

When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.

This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface.
Value Description
0x0 DISABLED
0x1 ENABLED
RO 0x0
17 pls 
PHY Link Status

This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER.
When set, the link is considered to be okay (up) and when reset, the link is considered to be down.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
16 lpien 
LPI Enable

When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. 

This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
15:10 reserved_15_10 
Reserved
 RO 0x0
9 rlpist 
Receive LPI State

When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
8 tlpist 
Transmit LPI State

When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
7:4 reserved_7_4 
Reserved
 RO 0x0
3 rlpiex 
Receive LPI Exit

When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register.

Note: 
This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
2 rlpien 
Receive LPI Entry

When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.

Note: 
This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
1 tlpiex 
Transmit LPI Exit

When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
0 tlpien 
Transmit LPI Entry

When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0