gmacgrp_target_time_seconds

         
The Target Time Seconds register, along with Target Time Nanoseconds register, is used to schedule an interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the system time exceeds the value programmed in these registers.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF80071C`
`i_emac_emac1`	`0xFF802000`	`0xFF80271C`
`i_emac_emac2`	`0xFF804000`	`0xFF80471C`

Size: 32

Offset: 0x71C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`tstr` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`tstr` `RW 0x0`

gmacgrp_target_time_seconds Fields

Bit	Name	Description	Access	Reset
31:0	`tstr`	This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled).	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

tstr

This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled).

RW

0x0