gmacgrp_interrupt_mask 

         <b> Register 15 (Interrupt Mask Register) </b> 

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o in the GMAC-AHB, GMAC-AXI, and GMAC-DMA configuration and mci_intr_o in the GMAC-MTL and GMAC-CORE configuration.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF80003C
i_emac_emac1 0xFF802000 0xFF80203C
i_emac_emac2 0xFF804000 0xFF80403C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_11

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_11

RO 0x0

lpiim

RW 0x0

tsim

RO 0x0

reserved_8_4

RO 0x0

pmtim

RW 0x0

pcsancim

RO 0x0

pcslchgim

RO 0x0

rgsmiiim

RO 0x0

gmacgrp_interrupt_mask Fields

Bit Name Description Access Reset
31:11 reserved_31_11 
Reserved
 RO 0x0
10 lpiim 
LPI Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register).
This bit is valid only when you select the Energy Efficient Ethernet feature during core configuration. In all other modes, this bit is reserved.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
9 tsim 
Timestamp Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register).
This bit is valid only when IEEE1588 timestamping is enabled. In all other modes, this bit is reserved.
Value Description
0x0 DISABLED
0x1 ENABLED
RO 0x0
8:4 reserved_8_4 
Reserved
 RO 0x0
3 pmtim 
PMT Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register).
 RW 0x0
2 pcsancim 
PCS AN Completion Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register).
RO 0x0
1 pcslchgim 
PCS Link Status Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register).
 RO 0x0
0 rgsmiiim 
RGMII or SMII Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register).
Value Description
0x0 DISABLED
0x1 ENABLED
RO 0x0