gmacgrp_layer3_addr2_reg2

         
For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF800478`
`i_emac_emac1`	`0xFF802000`	`0xFF802478`
`i_emac_emac2`	`0xFF804000`	`0xFF804478`

Size: 32

Offset: 0x478

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`l3a22` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`l3a22` `RW 0x0`

gmacgrp_layer3_addr2_reg2 Fields

Bit	Name	Description	Access	Reset
31:0	`l3a22`	When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and Layer 4 Control Register 2), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control Register 2), this register is not used.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

l3a22

When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames.

When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and Layer 4 Control Register 2), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames.

When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control Register 2), this register is not used.

RW

0x0