gmacgrp_mmc_control 

         <b> Register 64 (MMC Control Register) </b>

The MMC Control register establishes the operating mode of the management counters.

Note:
The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800100
i_emac_emac1 0xFF802000 0xFF802100
i_emac_emac2 0xFF804000 0xFF804100

Size: 32

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_9

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_9

RO 0x0

ucdbc

RW 0x0

reserved_7_6

RO 0x0

cntprstlvl

RW 0x0

cntprst

RW 0x0

cntfreez

RW 0x0

rstonrd

RW 0x0

cntstopro

RW 0x0

cntrst

RW 0x0

gmacgrp_mmc_control Fields

Bit Name Description Access Reset
31:9 reserved_31_9 
Reserved
 RO 0x0
8 ucdbc 
Update MMC Counters for Dropped Broadcast Frames

When set, this bit enables MAC to update all the related MMC Counters for Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of MAC Filter Register at offset 0x0004.
When reset, MMC Counters are not updated for dropped Broadcast frames.
 RW 0x0
7:6 reserved_7_6 
Reserved
 RO 0x0
5 cntprstlvl 
Full-Half Preset

When low and bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16).
When this bit is high and bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - 16).
For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.
Value Description
0x0 ALMOSTHALF
0x1 ALMOSTFULL
RW 0x0
4 cntprst 
Counters Preset

When this bit is set, all counters are initialized or preset to almost full or almost half according to bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
3 cntfreez 
MMC Counter Freeze

When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
2 rstonrd 
Reset on Read

When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (bits[7:0]) is read.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
1 cntstopro 
Counters Stop Rollover

When this bit is set, after reaching maximum value, the counter does not roll over to zero.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
0 cntrst 
Counters Reset

When this bit is set, all counters are reset. This bit is cleared automatically after one clock cycle.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0