dmagrp_status

Reserved

GMAC LPI Interrupt (for Channel 0) 

This bit indicates an interrupt event in the LPI logic of the DWC_gmac. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source.

Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved.When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high.

Timestamp Trigger Interrupt 

This bit indicates an interrupt event in the Timestamp Generator block of DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high.

This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved.

GMAC PMT Interrupt

This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. 

This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved.

Note: The GPI and pmt_intr_o interrupts are generated in different clock domains.

GMAC MMC Interrupt

This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of interrupt and clear the source of interrupt to make this bit as 1'b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high.

This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved.

GMAC Line interface Interrupt 
When set, this bit reflects any of the following interrupt events in the DWC_gmac
interfaces (if present and enabled in your configuration):
 * PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event
 * SMII or RGMII: Link change event
 * General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports
To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers:
 * PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register)
 * SMII or RGMII: Register 54 (SGMII/RGMII/SMII Status Register)
 * General Purpose Input (GPI): Register 56 (General Purpose IO Register)
The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high.

Error Bits
This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt.

 * 0 0 0: Error during Rx DMA Write Data Transfer
 * 0 1 1: Error during Tx DMA Read Data Transfer
 * 1 0 0: Error during Rx DMA Descriptor Write Access
 * 1 0 1: Error during Tx DMA Descriptor Write Access
 * 1 1 0: Error during Rx DMA Descriptor Read Access
 * 1 1 1: Error during Tx DMA Descriptor Read Access
 
Note: 001 and 010 are reserved.

Transmit Process State

This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 
 * 3'b000: Stopped; Reset or Stop Transmit Command issued
 * 3'b001: Running; Fetching Transmit Transfer Descriptor
 * 3'b010: Running; Waiting for status
 * 3'b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO)
 * 3'b100: TIME_STAMP write state
 * 3'b101: Reserved for future use
 * 3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow
 * 3'b111: Running; Closing Transmit Descriptor

Received Process State

This field indicates the Receive DMA FSM state. This field does not generate an interrupt.
 * 3'b000: Stopped: Reset or Stop Receive Command issued
 * 3'b001: Running: Fetching Receive Transfer Descriptor
 * 3'b010: Reserved for future use
 * 3'b011: Running: Waiting for receive packet
 * 3'b100: Suspended: Receive Descriptor Unavailable
 * 3'b101: Running: Closing Receive Descriptor
 * 3'b110: TIME_STAMP write state
 * 3'b111: Running: Transferring the receive packet data from receive buffer to host memory

Normal Interrupt Summary

Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):
 * Register 5[0]: Transmit Interrupt
 * Register 5[2]: Transmit Buffer Unavailable
 * Register 5[6]: Receive Interrupt
 * Register 5[14]: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit.

This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared.

Abnormal Interrupt Summary

Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):
 * Register 5[1]: Transmit Process Stopped
 * Register 5[3]: Transmit Jabber Timeout
 * Register 5[4]: Receive FIFO Overflow
 * Register 5[5]: Transmit Underflow
 * Register 5[7]: Receive Buffer Unavailable
 * Register 5[8]: Receive Process Stopped
 * Register 5[9]: Receive Watchdog Timeout
 * Register 5[10]: Early Transmit Interrupt
 * Register 5[13]: Fatal Bus Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.

This is a sticky bit and must be cleared each time a corresponding bit, which causes AIS to be set, is cleared.

Early Receive Interrupt

This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier).

Fatal Bus Error Interrupt

This bit indicates that a bus error occurred, as described in Bits[25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses.

Reserved

Early Transmit Interrupt

This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.

Receive Watchdog Timeout

When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout.

Receive Process Stopped

This bit is asserted when the Receive Process enters the Stopped state.

Receive Buffer Unavailable

This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.

Receive Interrupt

This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. 
The reception remains in the Running state.

Transmit Underflow

This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.

Receive Overflow

This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11].

Transmit Jabber Timeout

This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.

Transmit Buffer Unavailable

This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. 

To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command.

Transmit Process Stopped

This bit is set when the transmission is stopped.

Transmit Interrupt

This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor.