gmacgrp_mac_frame_filter

Receive All

When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. 

When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter.

Reserved

Drop non-TCP/UDP over IP Frames

When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. 

When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames.
If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value).

Layer 3 and Layer 4 Filter Enable

When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect.

When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields.

If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value).

Reserved

VLAN Tag Filter Enable

When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. 

When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag.

Reserved

Hash or Perfect Filter

When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. 

When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. This bit is reserved (and RO) if the Hash filter is not selected during core configuration.

Source Address Filter Enable

When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame.
When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.

Note: According to the IEEE specification, Bit 47 of the SA is reserved and set to 0. However, in DWC_gmac, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA.

SA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. 

When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter.

Pass Control Frames

These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). 
 * 00: MAC filters all control frames from reaching the application.
 * 01: MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 
 * 10: MAC forwards all control frames to application even if they fail the Address Filter.
 * 11: MAC forwards control frames that pass the Address Filter.
The following conditions should be true for the PAUSE control frames processing:
 * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
 * Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set.
 * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.

Note: 

This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE frames are considered as generic control frames. Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application).

Disable Broadcast Frames

When this bit is set, the AFM module filters all incoming broadcast frames. In addition, it overrides all other filter settings. 

When this bit is reset, the AFM module passes all received broadcast frames.

Pass All Multicast

When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. 

When reset, filtering of multicast frame depends on HMC bit.

DA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.

When reset, normal filtering of frames is performed.

Hash Multicast

When set, MAC performs destination address filtering of received multicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers.
If Hash Filter is not selected during core configuration, this bit is reserved (and RO).

Hash Unicast

When set, MAC performs destination address filtering of unicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers.

If Hash Filter is not selected during core configuration, this bit is reserved (and RO).

Promiscuous Mode

When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set.