dmagrp_missed_frame_and_buffer_overflow_counter

         <b>Register 8 (Missed Frame and Buffer Overflow Counter Register) </b>

The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF801020`
`i_emac_emac1`	`0xFF802000`	`0xFF803020`
`i_emac_emac2`	`0xFF804000`	`0xFF805020`

Size: 32

Offset: 0x1020

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`reserved_31_29` `RO 0x0`			`ovfcntovf` `RO 0x0`	`ovffrmcnt` `RO 0x0`											`miscntovf` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`misfrmcnt` `RO 0x0`

dmagrp_missed_frame_and_buffer_overflow_counter Fields

Bit	Name	Description	Access	Reset
31:29	`reserved_31_29`	Reserved	`RO`	`0x0`
28	`ovfcntovf`	Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.	`RO`	`0x0`
27:17	`ovffrmcnt`	Overflow Frame Counter This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1'b1.	`RO`	`0x0`
16	`miscntovf`	Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.	`RO`	`0x0`
15:0	`misfrmcnt`	Missed Frame Counter This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1'b1.	`RO`	`0x0`